Silicon Industry News

Latest news from the semiconductor industry

Understanding surface science to manufacture quality cosmetics

From phys.org:

A research team affiliated with UNIST has examined the rates of liquid penetration on rough or patterned surfaces, especially those with pores or cavities. Their findings provide important insights into the development of everyday products, including cosmetics and paints, and industrial applications like enhanced oil recovery.

This study has been jointly led by Professor Dong Woog Lee and his research team in the School of Energy and Chemical Engineering at UNIST and a research team at the University of California, Santa Barbara. Published online in the July 19th issue of the Proceedings of the National Academy of Sciences (PNAS), the study identifies five variables that control cavity-filling (wetting transition) rates, required for liquids to penetrate into cavities.

In the study, Professor Lee fabricated silicon wafers with cylindrical cavities of different geometries. After immersing them in bulk water, they observed the details of, and the rates associated with, water penetration into the cavities from the bulk, using bright-field and confocal fluorescence microscopy. Cylindrical cavities are like skin pores with narrow entrance and specious interior. The cavity filling generally progresses when bulk water is spread above a hydrophilic, reentrant cavity. As described in “Wetting Transition from the Cassie-Baxter State to Wenzel State,” the […]

September 18th, 2018|General News Feed|

TowerJazz showcasing SiGe and silicon photonic processes for 100-400Gb/s optical data links

By Semiconductor Today: 

In booth #569 at the 44th European Conference on Optical Communication (ECOC 2018) in Rome, Italy (23-27 September), specialty foundry TowerJazz (which has fabrication plants at Tower Semiconductor Ltd in Migdal Haemek, Israel, and at its US subsidiaries Jazz Semiconductor Inc in Newport Beach, CA and TowerJazz Texas Inc in San Antonio, TX, and at TowerJazz Japan Ltd) is showcasing its silicon germanium (SiGe) process, with speeds in excess of 300GHz, and its newest production SiPho (silicon photonics) process built into data-center high-speed optical data links.

TowerJazz claims that it has a significant foundry share of the 100Gb/s transceiver market served by its SiGe Terabit Platform, and it is showcasing even higher SiGe transistor speeds and patented features appropriate for 200 and 400Gb/s communication ICs such as transimpedance amplifiers (TIAs), laser and modulator drivers, and clock & data recovery circuits.

Read more: TowerJazz showcasing SiGe and silicon photonic processes for 100-400Gb/s optical data links reposted by Silicon Valley Microelectroncs, Inc. 

September 10th, 2018|General News Feed|

The electronic transistor you’ve been waiting for

From phys.org:

How do you pack more power into an electric car?

The answer may be electronic transistors made of gallium oxide, which could enable automakers to boost energy output while keeping vehicles lightweight and streamlined in design.

A recent advancement—reported in the September issue of the journal IEEE Electron Device Letters—illustrates how this evolving technology could play a key role improving electric vehicles, solar power and other forms of renewable energy.

“To advance these technologies, we need new electrical components with greater and more efficient power-handling capabilities,” says the study’s lead author Uttam Singisetti, Ph.D., associate professor of electrical engineering in UB’s School of Engineering and Applied Sciences. “Gallium oxide opens new possibilities that we cannot achieve with existing semiconductors.”

The most widely used semiconducting material is silicon. For years, scientists have relied upon it to manipulate greater amounts of power in electronic devices. But scientists are running out of ways to maximize silicon as semiconductor, which is why they’re exploring other materials such as silicon carbide, gallium nitride and gallium oxide.

While gallium oxide has poor thermal conductivity, its bandgap (about 4.8 electron volts) exceeds that of silicon carbide (about 3.4 electron volts), gallium nitride (about 3.3 electron volts) and silicon (1.1 electron volts).

Bandgap measures how much energy […]

September 10th, 2018|General News Feed|

Highly durable silicon carbide (SiC) power semiconductor TED-MOS for energy saving in electric vehicle motors

From TechXplore:

Hitachi, Ltd. today announced the development of an original energy saving power semiconductor structure, TED-MOS, using next-generation silicon carbide (SiC) material that contributes to saving energy in electric vehicles (EV). This power semiconductor is a new device using a fin-structured trench MOSFET based on the conventional DMOS-FET, a SiC transistor of power semiconductor. Using this new device, an energy saving of 50 percent was confirmed as the structure reduces the electric field strength, an index of durability, by 40 percent and resistance by 25 percent compared to the conventional DMOS-FET. Hitachi intends to apply this device in motor drive inverters which are a core component of EVs to increase energy efficiency. Furthermore, by utilizing this technology not only in EVs but also in a range of electrical transducers used in societal infrastructure systems, Hitachi hopes to contribute to efforts to reduce global warming and the realization of a low-carbon society.

With the anticipated increase in global energy demand, targets to reduce environmental load are being set through initiatives such as the SDGs and COP21 to realize a sustainable society. As the adoption of EVs is also expected to increase dramatically, reducing EV power consumption is considered critical, Thus, the use of […]

September 10th, 2018|General News Feed|

Helping the microchip industry go (very low) with the flow

From phys.org:

A new study by scientists at the National Institute of Standards and Technology (NIST) has uncovered a source of error in an industry-standard calibration method that could lead microchip manufacturers to lose a million dollars or more in a single fabrication run. The problem is expected to become progressively more acute as chipmakers pack ever more features into ever smaller space.

The error occurs when measuring very small flows of exotic gas mixtures. Small gas flows occur during chemical vapor deposition (CVD), a process that occurs inside a vacuum chamber when ultra-rarefied gases flow across a silicon wafer to deposit a solid film. CVD is widely used to fabricate many kinds of high-performance microchips containing as many as several billion transistors. CVD builds up complex 3-D structures by depositing successive layers of atoms or molecules; some layers are only a few atoms thick. A complementary process called plasma etching also uses small flows of exotic gases to produce tiny features on the surface of semiconducting materials by removing small amounts of silicon.

The exact amount of gas injected into the chamber is critically important to these processes and is regulated by a device called a mass flow controller (MFC). MFCs must be […]

August 22nd, 2018|General News Feed|

Fujitsu triples the output power of gallium-nitride transistors

From TechXplore:

Fujitsu Limited and Fujitsu Laboratories Ltd. today announced that they have developed a crystal structure that both increases current and voltage in gallium-nitride (GaN) high electron mobility transistors (HEMT), effectively tripling the output power of transistors used for transmitters in the microwave band. GaN HEMT technology can serve as a power amplifier for equipment such as weather radar. By applying the new technology to this area, it is expected that the observation range of the radar will be expanded by 2.3 times, enabling early detection of cumulonimbus clouds that can develop into torrential rainstorms.

To expand the observation range of equipment like radar, it is essential to increase the output power of the transistors used in power amplifiers. With conventional technology, however, applying high voltage could easily damage the crystals that compose a transistor. Therefore, it was technically difficult to increase current and voltage simultaneously, which is required to realize high-output power GaN HEMTs.

Fujitsu and Fujitsu Laboratories have now developed a crystal structure that improves operating voltage by dispersing the applied voltage to the transistor, and thereby prevents crystal damage (patent pending). This technology has enabled Fujitsu to successfully achieve the world’s highest power density at 19.9 watts per millimeter of gate width […]

August 22nd, 2018|General News Feed|

Re-interpreting Moore’s Law

From EE Journal:

EE Journal takes a look at the “end” of Moore’s law and what it means for semiconductor miniaturization and chip fabrication.

Read more: Re-interpreting Moore’s Law reposted by Silicon Valley Microelectronics.

August 9th, 2018|General News Feed|

Integrating capacitors into p-gallium nitride gate transistors on silicon

From Semiconductor Today:

Hong Kong University of Science and Technology (HKUST) and Taiwan Semiconductor Manufacturing Company Ltd have been jointly developing integrated capacitors for p-type gallium nitride (p-GaN) gate high-frequency power transistors on silicon substrate [Gaofei Tang et al, IEEE Electron Device Letters, published online 9 July 2018]. GaN transistors with a p-gate enable enhancement-mode operation where transistors are in the current-off state with zero gate potential. This reduces power consumption and allows fail-safe operation.

GaN transistors are being developed for high-frequency power applications with a view to high conversion efficiency and power density. Production on silicon should reduce manufacturing cost.

One problem with p-gate enhancement-mode transistors is parasitic inductance in the gate-drive loop causing over-voltage stress at high frequency. Parasitic inductance can be minimized by on-chip integration of high-voltage power switches and peripheral drive/control modules. Such integration is promoted by the availability of integrated passive devices – resistors and capacitors. Capacitors are used to help de-couple noise in the power supply, shift levels, and pump charge in the gate driver.

The material structure for the p-GaN gate capacitors was metal/p-GaN/AlGaN/GaN produced for commercial 650V enhancement-mode power devices. The capacitor used ohmic contacts on the n-side and a Schottky contact on the p-GaN […]

August 9th, 2018|General News Feed|

NASA studies space applications for GaN crystals

From Phys.org:

An exotic material poised to become the semiconductor of choice for power electronics —- because it is far more efficient than silicon—is now being eyed for potential applications in space.

Two NASA teams are examining the use of gallium nitride, a crystal-type semiconductor compound first discovered in the 1980s, and currently used in consumer electronics such as laser diodes in DVD readers. Among its many attributes, gallium nitride—GaN, for short—demonstrates less electrical resistance and thus loses only a small proportion of power as heat. The material can handle 10 times the electrical current of silicon, enabling smaller, faster, and more efficient devices. In addition, it’s tolerant to a wide range of temperatures, resistant to radiation, and as it turns out, adept at detecting energetic particles.

It’s no wonder then that scientists and engineers at NASA’s Goddard Space Flight Center in Greenbelt, Maryland, are interested in seeing how they could tap into this versatile material to enhance space exploration.

With their funding, engineer Jean-Marie Lauenstein and scientist Elizabeth MacDonald are investigating Gallium-Nitride High Electron Mobility Transistors, or GaN HEMTs, for use in studying how Earth’s magnetosphere couples to its ionosphere—a key question in the field of heliophysics, which among other things studies the forces […]

August 7th, 2018|General News Feed|

Generation of random numbers by measuring phase fluctuations from a laser diode with a silicon-on-in

From phys.org:

Researchers have shown that a chip-based device measuring a millimeter square could be used to generate quantum-based random numbers at gigabit per second speeds. The tiny device requires little power and could enable stand-alone random number generators or be incorporated into laptops and smart phones to offer real-time encryption.

“While part of the control electronics is not integrated yet, the device we designed integrates all the required optical components on one chip,” said first author Francesco Raffaelli, University of Bristol, United Kingdom. “Using this device by itself or integrating it into other portable devices would be very useful in the future to make our information more secure and to better protect our privacy.”

Random number generators are used to encrypt data transmitted during digital transactions such as buying products online or sending a secure e-mail. Today’s random number generators are based on computer algorithms, which can leave data vulnerable if hackers figure out the algorithm used.

In The Optical Society (OSA) journal Optics Express, the researchers report a quantum random number generator based on randomly emitted photons from a diode laser. Because the photon emission is inherently random, it is impossible to predict the numbers that will be generated.

“Compared to other integrated […]

July 24th, 2018|General News Feed|

Rising microchip-maker demand boosts ASML profits

From phys.org:

Dutch global hi-tech bellwether ASML Wednesday posted a huge hike in second quarter profits, after the technology industry snapped up more of its sophisticated microchip-making machines than expected.

Profits rose 25 percent year-on-year to 584 million euros ($679 million), up from 466 million in the same quarter in 2017.

“Our second quarter sales were above expectations including higher than forecasted EUV sales,” said chief executive Peter Wennink, referring to the company’s cutting-edge extreme ultraviolet light lithography machines.

The company, based in Veldhoven, revealed it had shipped four of the massive machines in the second quarter, one more than expected, with each selling for around 120 million euros.

It is on track to sell around 20 EUV machines this year, with plans for 30 more in 2019.

That pushed second quarter sales to 2.7 billion euros up from 2.1 billion euros in the same period in 2017.

“After an excellent first half of 2018, we expect the second half to be stronger, with improved profitability and continued growth from Q3 to Q4,” Wennink said.

ASML is one of the world’s leading makers of lithography systems used by the semiconductor industry to make integrated circuits and microchips.

The company is considered a bellwether of the global high-tech industry as it supplies sector […]

July 24th, 2018|General News Feed|

Better understanding the principles of silicon etching leads to improved surface patterning

From Phys Org:

From solar cells that capture more light, to medical devices that resist colonization by bacteria; there are many applications for materials given a bristly coating of silicon nanowires. Creating these nanostructured silicon surfaces can be challenging—but A*STAR researchers have now discovered how to control at least one route.

Metal-assisted chemical etching (MacEtch) is one of the most scalable and cost-effective ways to form these surfaces, but researchers frequently encounter discrepancies between existing MacEtch models and the process in reality.
Sing Yang Chiam at the A*STAR Institute of Materials Research and Engineering and his colleagues have now discovered the key governing mechanism by which MacEtch works. “We were very surprised by our discoveries,” says Chiam. “Only after many repeated tests, and studying it from many angles, did we become convinced by our model.”

Read more at: Better understanding the principles of silicon etching leads to improved surface patterning reposted by Silicon Valley Microelectronics Inc. 

July 19th, 2018|General News Feed|

A simple method etches patterns at the atomic scale

From Phys Org:

A precise, chemical-free method for etching nanoscale features on silicon wafers has been developed by a team from Penn State and Southwest Jiaotong University and Tsinghua University in China.

In standard lithography, a photosensitive film is deposited on a silicon wafer and a pattern called a mask is used to expose certain portions of the film. Then, chemicals—such as a potassium hydroxide solution—etch patterns into the silicon. Further steps are required to smooth out the roughened surface.
The Penn State and Southwest Jiaotong University researchers developed an entirely different, chemical- and mask-free, one-step process. They lightly rubbed a rounded silica tip of an instrument called a scanning probe microscope across a silicon substrate—the material base typically used to make electronic devices. When exposed to the water vapor in air, the top layer of silicon forms bonds with the tip of the scanning probe, and a single layer of atoms slides off as the probe moves across the silicon. Because the atoms below do not take part in the chemical reaction, they are completely undamaged.

Read more at: A simple method etches patterns at the atomic scale reposted by Silicon Valley Microelectronics. 

July 19th, 2018|General News Feed|

SILTECTRA reports application of COLD SPLIT wafer thinning technology to GaAs

From Semiconductor Today:

At the SEMICON West 2018 tradeshow and conference in San Francisco (10-12 July), wafering technology firm SILTECTRA GmbH of Dresden, Germany has revealed new enabling and cost-of-ownership (CoO) advantages for its COLD SPLIT laser-based wafer thinning technology. Collectively, the benefits aim to further enable manufacturers of power semiconductors.

Enabling wafering solution for diverse materials

In the latest demonstration of COLD SPLIT’s capabilities, SILTECTRA says that, when applied to gallium arsenide (GaAs), COLD SPLIT achieved the same thinness and near-zero material loss as previously shown for silicon carbide (SiC), gallium nitride (GaN), sapphire and silicon.

The data comes from a recent study (funded by the State Government of Saxony) to establish if COLD SPLIT could achieve full crack propagation across the laser plane when applied to GaAs. Participants included a leading materials supplier and a renowned laser institute, as well as SILTECTRA. The results validated COLD SPLIT as a high-performance thinning solution for GaAs and demonstrated that the technique can thin a range of diverse materials with complex properties.

Read more: SILTECTRA reports application of COLD SPLIT wafer thinning technology to GaAs reposted by Silicon Valley Microelectronics, Inc. 

July 17th, 2018|General News Feed|

SEMICON West 2018: Imec and Soitec Demonstrate Sequential 3D Planar Device with High Reliability at Low Temperature | Electronics360

From Electronics 360:

Imec, in collaboration with Soitec, announced a successful sequential 3D front-end integration process by stacking two device layers on one another on a 300 mm wafer. The debut occurred at the annual Imec Technology Forum USA.

This vertical integration process, also named sequential-3D integration (S3D), promises to continue the benefits offered by semiconductor scaling, overcoming the constraints of geometrical scaling while maintaining the benefits of functional scaling through the vertical 3D integration.

A critical challenge of S3D is the control of the thermal budget. To preserve optimal device operation the top device layer must be processed at temperatures below 525° C. The top thermal budget needs to be reduced to avoid degradation of the bottom devices, the bottom interconnects and the bonding interface. These limitations are overcome with the implementation of junction-less transistors on the top-layer which decreases the fabrication complexity and provides sufficient device reliability.

Read more: SEMICON West 2018: Imec and Soitec Demonstrate Sequential 3D Planar Device with High Reliability at Low Temperature | Electronics360 reposted by Silicon Valley Microelectronics, Inc. 

July 17th, 2018|General News Feed|

Acacia launches ZR-class coherent CFP and CFP2 DCO pluggable modules

From Semiconductor Today

Acacia Communications Inc of Maynard, MA, USA has announced the general availability of two new high-speed coherent optical interconnect products for ZR applications. Enabled by Acacia’s low-power, highly integrated designs that leverage its proprietary digital signal processor (DSP) and silicon photonic technologies, the firm believes that its new 100G/200G CFP2-DCO ZR and next-generation low-power 100G CFP-DCO ZR will address demands for growing capacity in network access, edge and enterprise campus applications.

The new products support the requirements of unamplified applications beyond the 40km reaches standardized in the industry and extend to 80km and beyond. The CFP-DCO ZR module is capable of supporting the 18W power class that has been widely deployed for 10km client applications. Both modules also offer high-capacity and low-power-consumption solutions designed to reduce the complexity, power usage and cost of high-bandwidth interconnects.

“Based on our experience with network operators, we see increasing demand for 100G and above in access aggregation markets,” comments Jimmy Mizrahi, VP global portfolio at ECI Telecon Ltd. “Coherent 100G and 200G ZR solutions, in compact pluggable form factors, will be an attractive solution for network operators with requirements for reaches greater than 40km in applications such as 5G backhaul and cable access,” […]

July 16th, 2018|General News Feed|

Leti and Soitec launch a substrate innovation centre

From New Electronics:

Leti, a research institute of CEA Tech, and Soitec, a specialist in designing and manufacturing innovative semiconductor materials, have announced that they will be collaborating. as part of a five-year partnership agreement, to drive research into advanced engineered substrates, including SOI and beyond.

The agreement includes the launch of a new world-class prototyping hub that will bring together equipment partners with new materials, The Substrate Innovation Center will feature access to shared Leti-Soitec expertise around a focused pilot line. Key benefits will include access to early exploratory sampling and prototyping, collaborative analysis, and early learning at the substrate level, with the aim of eventually leading to streamlined product viability and roadmap planning at the system level.

Leading chip makers and foundries worldwide use Soitec products to manufacture chips for applications such as smart phones, data centres, automotive, imagers, and medical and industrial equipment. The Substrate Innovation Center, to be located on Leti’s campus, will enable engineers to explore and develop innovative substrate features, with a special focus on 4G/5G connectivity, artificial intelligence, sensors and display, automotive, photonics, and edge computing.

“Material innovation and substrate engineering make entire new horizons possible. The Substrate Innovation Center will unleash the power of substrate […]

July 12th, 2018|General News Feed|

Generating electrical power from waste heat

From phys.org:

Directly converting electrical power to heat is easy. It regularly happens in your toaster, that is, if you make toast regularly. The opposite, converting heat into electrical power, isn’t so easy.

Researchers from Sandia National Laboratories have developed a tiny silicon-based device that can harness what was previously called waste heat and turn it into DC power. Their advance was recently published in Physical Review Applied.

“We have developed a new method for essentially recovering energy from waste heat. Car engines produce a lot of heat and that heat is just waste, right? So imagine if you could convert that engine heat into electrical power for a hybrid car. This is the first step in that direction, but much more work needs to be done,” said Paul Davids, a physicist and the principal investigator for the study.

“In the short term we’re looking to make a compact infrared power supply, perhaps to replace radioisotope thermoelectric generators.” Called RTGs, the generators are used for such tasks as powering sensors for space missions that don’t get enough direct sunlight to power solar panels.

Davids’ device is made of common and abundant materials, such as aluminum, silicon and silicon dioxide—or glass—combined in very uncommon ways.

Silicon device catches, channels and converts heat into power

Smaller than […]

July 9th, 2018|General News Feed|

Monolithic indium phosphide on silicon growth for optoelectronics

From Semiconductor Today:

Hong Kong University of Science and Technology (HKUST) has been advancing technologies for direct growth of indium phosphide (InP) on silicon (Si) substrate with a view to monolithic integration of optoelectronics on a low-cost platform.

In particular, professor Kei May Lau’s group at HKUST claims the first indium gallium arsenide/indium aluminium gallium arsenide (InGaAs/InAlGaAs multi-quantum-well (MQW) lasers directly grown on on-axis V-grooved (001) Si by metal-organic chemical vapor deposition (MOCVD) [Si Zhu et al, Optics Express, vol26, p14514, 2018]. Miscut silicon substrates are often used to grow III-V materials to avoid defects such as anti-phase boundaries.

Integration of lasers with on-axis silicon is desired for the interconnection of photonic integrated circuits and optical-fiber large-scale networking with the efficient, complex complementary metal-oxide-semiconductor (CMOS) electronics that powers today’s communications technologies. Monolithic integration, it is hoped, will reduce the costs arising from additional processing needed for wafer bonding, and also allow the use of larger-diameter substrates for economies of scale.

Read more: Monolithic indium phosphide on silicon growth for optoelectronics reposted by Silicon Valley Microelectronics, Inc. 

July 9th, 2018|General News Feed|

Undoped gallium nitride upper waveguide for reduced laser threshold

From Semiconductor Today:

Researchers in China have used an undoped gallium nitride (u-GaN) upper waveguide (WG) to reduce the threshold current density for an indium gallium nitride (InGaN) laser diode (LD) [Feng Liang et al, Jpn. J. Appl. Phys., vol57, p070307, 2018].

The u-GaN waveguide was positioned between the last quantum barrier of the multiple quantum well active region of the device and the p-type aluminium gallium nitride (p-AlGaN) electron-blocking layer (EBL). This reverses the conventional order for III-nitride laser diodes (Figure 1). The use of an undoped rather than doped GaN waveguide reduced optical losses, allowing lasing to occur at lower current injection. The upper waveguide layer confines the optical field away from the lossy p-type regions. Also, the new structure with u-GaN upper waveguide avoids diffusion of dopants into the active region, which also saps recombination into photons.

The research team included engineering scientists from Institute of Semiconductors, University of Chinese Academy of Sciences, Suzhou Institute of Nano-tech and Nano-bionics, Microsystem and Terahertz Research Center, and Jilin University. The researchers see III-N laser diode applications in high-density optical data storage, optical coherence tomography, small portable projectors, and laser-based TVs.

Table 1: Target structural parameters of LD I and LD II.

Layer
Thickness
Doping level […]

July 9th, 2018|General News Feed|

Platform for fully vertical gallium nitride on silicon power devices

From Semiconductor Today: 

Massachusetts Institute of Technology (MIT) in the USA and Enkris Semiconductor Inc in China claim record performance for vertical gallium nitride (GaN) power diodes on foreign substrate [Yuhao Zhang et al, IEEE Electron Device Letters, published online 26 March 2018]. The researchers have developed a new platform for vertical GaN on silicon (Si) that creates a back-side trench, allowing a back contact to be made to the n-GaN layers.

The trench etching removes resistive buffer layers that have up to now mainly restricted GaN/Si power electronics to lateral or quasi-vertical structures with all contacts on the top side of epitaxial structures. The buffer layers are needed to bridge the lattice and thermal expansion mismatch between the foreign substrate and the GaN crystal structure. Fully vertical GaN power devices have generally been demonstrated on very expensive bulk or free-standing GaN substrates.

Vertical power devices are attractive because they push peak electric fields away from the surfaces and associated electron states that can cause premature breakdown. Vertical structures hence allow higher currents and voltages in more compact footprints. Also, lateral/quasi-vertical devices suffer from current crowding, which increases Joule heating.

Read more: Platform for fully vertical gallium nitride on silicon power devices, reposted […]

July 6th, 2018|General News Feed|

Semiconductor Engineering: Temporary Bonding: Enabling the Next Generation of Ultrathin Wafers

From Semiconductor Engineering:

Innovative materials are critical for maintaining integrity during advanced semiconductor manufacturing processes. Temporary bonding is being enabled by these new materials and is making a name for itself in the next generation of ultrathin wafer manufacturing.

Semiconductor wafers are being forced to become thinner as the push to shrink feature sizes and introduce full-scale 3D integration continues to grow.

While grinding wafers to less than 100 micrometers in thickness is a readily available process, moving to even thinner wafers (<50 µm) makes them exceedingly fragile. The stress of these extreme thinning processes and subsequent downstream metallization can cause additional stress on ultrathin wafers, contributing to warp or breakage.

The thin wafer handling process consists of temporarily mounting a device wafer to a carrier wafer with a polymeric bonding material system. This process is used to stabilize a wafer through harsh back-end processes while supporting the ultrathin device substrate. Two of the fastest growing release methods for debonding the wafer pairs are the laser and mechanical methods.

Source: Semiconductor Engineering: Temporary Bonding: Enabling the Next Generation of Ultrathin Wafers reposted by Silicon Valley Microelectronics, Inc. 

July 5th, 2018|General News Feed|

Semiconductor Engineering .:. Design Automation For Silicon Photonics: Pushing Research Into Production

From Semiconductor Engineering: 

Silicon photonics is a transformative technology that will have a major impact on system architectures in future IC design applications. Already a major solution for Datacom applications and emerging applications in sensing, design techniques in silicon photonics, with the ability to leverage CMOS technology to integrate large numbers of photonic components, are now being applied to enable optical computing. In almost all of these applications, however, an electrical interface is required, not just to provide modulation and detection signals, but to deliver real-time tuning to overcome manufacturing variability and temperature sensitivity inherent to silicon photonic components. In many cases, the supporting electrical connectivity and requisite I/O become dominant in the overall design process which includes floor-planning and physical implementation in photonic applications. Design tools, particularly tools for photonic circuit automation, need to be jointly aware of both the photonics and the electronics.

I’ve had a front row seat to development of design tools for photonics over the past seven years. It started with my involvement in a silicon photonics workshop in 2011. At that time, photonic workshops consisted of academics and researchers spending a week learning all the necessary details on every aspect of silicon photonic design, ranging […]

July 5th, 2018|General News Feed|

Monolithic indium phosphide on silicon growth for optoelectronics

From Semiconductor Today: 

Hong Kong University of Science and Technology (HKUST) has been advancing technologies for direct growth of indium phosphide (InP) on silicon (Si) substrate with a view to monolithic integration of optoelectronics on a low-cost platform.

In particular, professor Kei May Lau’s group at HKUST claims the first indium gallium arsenide/indium aluminium gallium arsenide (InGaAs/InAlGaAs multi-quantum-well (MQW) lasers directly grown on on-axis V-grooved (001) Si by metal-organic chemical vapor deposition (MOCVD) [Si Zhu et al, Optics Express, vol26, p14514, 2018]. Miscut silicon substrates are often used to grow III-V materials to avoid defects such as anti-phase boundaries.

Integration of lasers with on-axis silicon is desired for the interconnection of photonic integrated circuits and optical-fiber large-scale networking with the efficient, complex complementary metal-oxide-semiconductor (CMOS) electronics that powers today’s communications technologies. Monolithic integration, it is hoped, will reduce the costs arising from additional processing needed for wafer bonding, and also allow the use of larger-diameter substrates for economies of scale.

The V-groove Si was created by etching with potassium hydroxide solution through a silicon dioxide (SiO2) mask. The parallel stripes were made with a 130nm pitch. The silicon surface was prepared for MOCVD with 800°C thermal desorption of native oxide.

Read more: Monolithic indium […]

July 3rd, 2018|General News Feed|

TowerJazz announces RF SOI 65nm ramp in 300mm Japan fab

From Semiconductor Today:

Specialty foundry TowerJazz (which has fabrication plants at Tower Semiconductor Ltd in Migdal Haemek, Israel, and at its US subsidiaries Jazz Semiconductor Inc in Newport Beach, CA and TowerJazz Texas Inc in San Antonio, TX, and at TowerJazz Japan Ltd) has announced a ramp for its radio-frequency silicon-on-insulator (RF SOI) 65nm process in its 300mm fab in Uozu, Japan. TowerJazz has signed a contract with long-term partner SOITEC of Bernin, near Grenoble, France (which makes engineered substrates including SOI wafers) to guarantee a supply of tens of thousands of 300mm SOI silicon wafers, securing wafer prices for the next few years and ensuring supply to its customers, despite a very tight SOI wafer market.

“We are delighted to see the strong adoption of 300mm RF SOI through this large capacity and supply agreement with TowerJazz to augment our already significant 200mm RF SOI partnership,” says SOITEC’s CEO Paul Boudre. “TowerJazz was the first foundry to ramp our RFeSI products to high-volume production in 200mm,” he adds.

With what are claimed to be best-in-class metrics, TowerJazz’s 65nm RF SOI process enables the combination of low-insertion-loss and high-power-handling RF switches with options for high-performance low-noise amplifiers (LNAs) as well as digital […]

July 3rd, 2018|General News Feed|

44GHz silicon switches offer industry’s lowest insertion loss

From New Electronics: 
Analog Devices has released 44GHz single-pole, double-throw (SPDT) switches, the ADRF5024 and ADRF5025 in advanced Silicon-on-Insulator (SOI) technology.
The switches are broadband, with the ADRF5024 yielding flat frequency response from 100MHz to 44GHz, while the ADRF5025 from 9kHz to 44GHz, with repeatable characteristics better than 1.7dB insertion loss and 35dB channel to channel isolation.

Both parts support 27dBm power handling for both through and hot-switching conditions. The new switches come in a compact, 2.25mm x 2.25mm surface-mount-technology (SMT) compatible package, which will benefit radio frequency (RF) and microwave design experts, saving bias power, eliminating peripheral components and achieving higher integration in systems such as phased arrays, portable instrumentation, high resolution body scanners and next generation millimeter-wave communication infrastructure for emerging 5G and high-constellation satellite networks.

Read more: 44GHz silicon switches offer industry’s lowest insertion loss reposted by Silicon Valley Microelectronics, Inc. 

July 2nd, 2018|General News Feed|

Schottky diodes integrated in vertical gallium nitride transistors on silicon

From Semiconductor Today:

École Polytechnique Fédérale de Lausanne (EPFL) in Switzerland claims the first monolithic integration of vertical gallium nitride (GaN) metal-oxide-semiconductor field-effect transistors (MOSFETs) with freewheeling Schottky barrier diodes (SBD) grown on 6-inch silicon substrates by metal-organic chemical vapor deposition [Chao Liu et al, IEEE Electron Device Letters, published online 1 June 2018]. This builds on previous work [www.semiconductor-today.com/news_items/2018/jan/epfl_160118.shtml].

The researchers hope to find a lower-cost route to vertical GaN power devices than the very expensive processes based on high-price bulk or free-standing GaN substrates that are presently used in research. GaN substrates are used to avoid defects that reduce the critical electric field for breakdown. Vertical power devices should be able to handle higher voltages and currents than lateral architectures. The use of large-diameter silicon substrates should reduce costs, but growth of GaN on silicon tends to introduce many performance-killing defects.

Freewheeling diodes are used in power conversion applications to allow the flow of reverse-bias current in the off state, releasing energy stored in inductive elements. While the in-built body p-i-n diode of the EPFL structure does allow some current flow, the turn-on voltage is high, increasing losses during switching. SBDs have a much lower turn-on voltage, along with faster […]

June 29th, 2018|General News Feed|

Wafer demand for ‘More than Moore’ devices to grow by 10%, says Yole Développement

From New Electronics:
Wafer demand for ‘More than Moore’ (MtM) devices is expected to grow by 10% between 2017 and 2023, Yole Développement, the market research and strategy consulting company, reports.
Driven by the adoption of evermore electronic components in end products, the semiconductor industry is facing a new era, Yole claims. Device scaling and cost reduction will no longer continue on the path followed for the past few decades. Instead, semiconductor companies are seeking solutions that bridge the gap between cost and performance, whilst adding increased functionality through integration.

MtM devices (including MEMS & sensors, CMOS Image Sensors, power electronic, along with RF devices) represent this functional diversification of technologies, the report continues, combining performance, integration and cost – not limited to CMOS scaling. And their importance, Yole predicts, will become greater.

MtM devices reached almost 45million 8-inch eq wafers in 2017 and the demand is anticipated to reach more than 66m 8-inch eq wafers by 2023.

According to the report, 6-inch and 8-inch are forecast to represent more than 60% of MtM wafers’ total wafer consumption. However, Yole says 12-inch will represent the fastest growth between 2017 and 2023, with demand growing from 3.3m units to 7.5m by 2023. This is due […]

June 29th, 2018|General News Feed|

Thiol molecules drive gold atoms to form a forest of nanowires with useful properties

Adjustments to sulfur-containing molecules have enabled researchers to precisely control the growth of gold nanowires, which are potentially useful in various applications including biosensors and catalysis.

Ligand molecules are used to prevent nanostructures from growing too large, or forming unwanted shapes. Suzhu Yu of the A*STAR Singapore Institute of Manufacturing Technology and colleagues had previously found that sulfur-containing molecules called thiols, which bind to gold, could be used to grow very thin gold nanowires. Now they have investigated how exactly these thiols do their job, and shown that different types of thiols can fine-tune the shape and size of the nanowires.

The researchers attached gold particles a few nanometers wide to a wafer of silicon, and then dipped this assembly into a solution containing a gold compound, a thiol ligand, and a reducing agent that generated gold atoms. When they used a ligand called 4-mercaptobenzoic acid (4-MBA), the nanoparticles sprouted a forest of gold nanowires that were 6 nanometers across and about 1 micrometer long in 15 minutes (see image).

The ligand binds strongly to any exposed part of the gold nanowire, and interactions between ligand molecules keep them densely packed on the wire’s surface. This prevents gold atoms in solution from sticking to the sides of the […]

June 25th, 2018|General News Feed|

What Happened To Selective Deposition?

From Semiconductor Engineering:

For years, the industry has been working on an advanced technology called area-selective deposition for chip production at 5nm and beyond.

Area-selective deposition, an advanced self-aligned patterning technique, is still in R&D amid a slew of challenges with the technology. But the more advanced forms of technology are beginning to make some progress, possibly inching closer from the lab to the fab.

The concept behind the technology isn’t new. For decades, chipmakers have used deposition, a process that deposits a blanket of materials on a surface. In area-select deposition, though, the idea is to use atomic layer deposition (ALD) to deposit materials in exact places. Using a bottoms-up approach, area-selective deposition, sometimes called area-selective ALD, is used to pattern and self-align tiny features on devices. Potentially, it could reduce the number of lithography and etch steps in the manufacturing flow.

For years the industry has used various forms of selective deposition in the fab to deposit metal materials on metal surfaces in devices. But for the more advanced forms of area-selective deposition, a tool must deposit different combinations of material sets in chips, such as metals on dielectrics, dielectrics on metals and dielectrics on dielectrics.

That’s the big stumbling block in R&D and the fab. For these […]

June 25th, 2018|General News Feed|