Silicon Industry News

Latest news from the semiconductor industry

SILTECTRA reports application of COLD SPLIT wafer thinning technology to GaAs

From Semiconductor Today:

At the SEMICON West 2018 tradeshow and conference in San Francisco (10-12 July), wafering technology firm SILTECTRA GmbH of Dresden, Germany has revealed new enabling and cost-of-ownership (CoO) advantages for its COLD SPLIT laser-based wafer thinning technology. Collectively, the benefits aim to further enable manufacturers of power semiconductors.

Enabling wafering solution for diverse materials

In the latest demonstration of COLD SPLIT’s capabilities, SILTECTRA says that, when applied to gallium arsenide (GaAs), COLD SPLIT achieved the same thinness and near-zero material loss as previously shown for silicon carbide (SiC), gallium nitride (GaN), sapphire and silicon.

The data comes from a recent study (funded by the State Government of Saxony) to establish if COLD SPLIT could achieve full crack propagation across the laser plane when applied to GaAs. Participants included a leading materials supplier and a renowned laser institute, as well as SILTECTRA. The results validated COLD SPLIT as a high-performance thinning solution for GaAs and demonstrated that the technique can thin a range of diverse materials with complex properties.

Read more: SILTECTRA reports application of COLD SPLIT wafer thinning technology to GaAs reposted by Silicon Valley Microelectronics, Inc. 

July 17th, 2018|General News Feed|

SEMICON West 2018: Imec and Soitec Demonstrate Sequential 3D Planar Device with High Reliability at Low Temperature | Electronics360

From Electronics 360:

Imec, in collaboration with Soitec, announced a successful sequential 3D front-end integration process by stacking two device layers on one another on a 300 mm wafer. The debut occurred at the annual Imec Technology Forum USA.

This vertical integration process, also named sequential-3D integration (S3D), promises to continue the benefits offered by semiconductor scaling, overcoming the constraints of geometrical scaling while maintaining the benefits of functional scaling through the vertical 3D integration.

A critical challenge of S3D is the control of the thermal budget. To preserve optimal device operation the top device layer must be processed at temperatures below 525° C. The top thermal budget needs to be reduced to avoid degradation of the bottom devices, the bottom interconnects and the bonding interface. These limitations are overcome with the implementation of junction-less transistors on the top-layer which decreases the fabrication complexity and provides sufficient device reliability.

Read more: SEMICON West 2018: Imec and Soitec Demonstrate Sequential 3D Planar Device with High Reliability at Low Temperature | Electronics360 reposted by Silicon Valley Microelectronics, Inc. 

July 17th, 2018|General News Feed|

Acacia launches ZR-class coherent CFP and CFP2 DCO pluggable modules

From Semiconductor Today

Acacia Communications Inc of Maynard, MA, USA has announced the general availability of two new high-speed coherent optical interconnect products for ZR applications. Enabled by Acacia’s low-power, highly integrated designs that leverage its proprietary digital signal processor (DSP) and silicon photonic technologies, the firm believes that its new 100G/200G CFP2-DCO ZR and next-generation low-power 100G CFP-DCO ZR will address demands for growing capacity in network access, edge and enterprise campus applications.

The new products support the requirements of unamplified applications beyond the 40km reaches standardized in the industry and extend to 80km and beyond. The CFP-DCO ZR module is capable of supporting the 18W power class that has been widely deployed for 10km client applications. Both modules also offer high-capacity and low-power-consumption solutions designed to reduce the complexity, power usage and cost of high-bandwidth interconnects.

“Based on our experience with network operators, we see increasing demand for 100G and above in access aggregation markets,” comments Jimmy Mizrahi, VP global portfolio at ECI Telecon Ltd. “Coherent 100G and 200G ZR solutions, in compact pluggable form factors, will be an attractive solution for network operators with requirements for reaches greater than 40km in applications such as 5G backhaul and cable access,” […]

July 16th, 2018|General News Feed|

Leti and Soitec launch a substrate innovation centre

From New Electronics:

Leti, a research institute of CEA Tech, and Soitec, a specialist in designing and manufacturing innovative semiconductor materials, have announced that they will be collaborating. as part of a five-year partnership agreement, to drive research into advanced engineered substrates, including SOI and beyond.

The agreement includes the launch of a new world-class prototyping hub that will bring together equipment partners with new materials, The Substrate Innovation Center will feature access to shared Leti-Soitec expertise around a focused pilot line. Key benefits will include access to early exploratory sampling and prototyping, collaborative analysis, and early learning at the substrate level, with the aim of eventually leading to streamlined product viability and roadmap planning at the system level.

Leading chip makers and foundries worldwide use Soitec products to manufacture chips for applications such as smart phones, data centres, automotive, imagers, and medical and industrial equipment. The Substrate Innovation Center, to be located on Leti’s campus, will enable engineers to explore and develop innovative substrate features, with a special focus on 4G/5G connectivity, artificial intelligence, sensors and display, automotive, photonics, and edge computing.

“Material innovation and substrate engineering make entire new horizons possible. The Substrate Innovation Center will unleash the power of substrate […]

July 12th, 2018|General News Feed|

Generating electrical power from waste heat

From phys.org:

Directly converting electrical power to heat is easy. It regularly happens in your toaster, that is, if you make toast regularly. The opposite, converting heat into electrical power, isn’t so easy.

Researchers from Sandia National Laboratories have developed a tiny silicon-based device that can harness what was previously called waste heat and turn it into DC power. Their advance was recently published in Physical Review Applied.

“We have developed a new method for essentially recovering energy from waste heat. Car engines produce a lot of heat and that heat is just waste, right? So imagine if you could convert that engine heat into electrical power for a hybrid car. This is the first step in that direction, but much more work needs to be done,” said Paul Davids, a physicist and the principal investigator for the study.

“In the short term we’re looking to make a compact infrared power supply, perhaps to replace radioisotope thermoelectric generators.” Called RTGs, the generators are used for such tasks as powering sensors for space missions that don’t get enough direct sunlight to power solar panels.

Davids’ device is made of common and abundant materials, such as aluminum, silicon and silicon dioxide—or glass—combined in very uncommon ways.

Silicon device catches, channels and converts heat into power

Smaller than […]

July 9th, 2018|General News Feed|

Monolithic indium phosphide on silicon growth for optoelectronics

From Semiconductor Today:

Hong Kong University of Science and Technology (HKUST) has been advancing technologies for direct growth of indium phosphide (InP) on silicon (Si) substrate with a view to monolithic integration of optoelectronics on a low-cost platform.

In particular, professor Kei May Lau’s group at HKUST claims the first indium gallium arsenide/indium aluminium gallium arsenide (InGaAs/InAlGaAs multi-quantum-well (MQW) lasers directly grown on on-axis V-grooved (001) Si by metal-organic chemical vapor deposition (MOCVD) [Si Zhu et al, Optics Express, vol26, p14514, 2018]. Miscut silicon substrates are often used to grow III-V materials to avoid defects such as anti-phase boundaries.

Integration of lasers with on-axis silicon is desired for the interconnection of photonic integrated circuits and optical-fiber large-scale networking with the efficient, complex complementary metal-oxide-semiconductor (CMOS) electronics that powers today’s communications technologies. Monolithic integration, it is hoped, will reduce the costs arising from additional processing needed for wafer bonding, and also allow the use of larger-diameter substrates for economies of scale.

Read more: Monolithic indium phosphide on silicon growth for optoelectronics reposted by Silicon Valley Microelectronics, Inc. 

July 9th, 2018|General News Feed|

Undoped gallium nitride upper waveguide for reduced laser threshold

From Semiconductor Today:

Researchers in China have used an undoped gallium nitride (u-GaN) upper waveguide (WG) to reduce the threshold current density for an indium gallium nitride (InGaN) laser diode (LD) [Feng Liang et al, Jpn. J. Appl. Phys., vol57, p070307, 2018].

The u-GaN waveguide was positioned between the last quantum barrier of the multiple quantum well active region of the device and the p-type aluminium gallium nitride (p-AlGaN) electron-blocking layer (EBL). This reverses the conventional order for III-nitride laser diodes (Figure 1). The use of an undoped rather than doped GaN waveguide reduced optical losses, allowing lasing to occur at lower current injection. The upper waveguide layer confines the optical field away from the lossy p-type regions. Also, the new structure with u-GaN upper waveguide avoids diffusion of dopants into the active region, which also saps recombination into photons.

The research team included engineering scientists from Institute of Semiconductors, University of Chinese Academy of Sciences, Suzhou Institute of Nano-tech and Nano-bionics, Microsystem and Terahertz Research Center, and Jilin University. The researchers see III-N laser diode applications in high-density optical data storage, optical coherence tomography, small portable projectors, and laser-based TVs.

Table 1: Target structural parameters of LD I and LD II.

Layer
Thickness
Doping level […]

July 9th, 2018|General News Feed|

Platform for fully vertical gallium nitride on silicon power devices

From Semiconductor Today: 

Massachusetts Institute of Technology (MIT) in the USA and Enkris Semiconductor Inc in China claim record performance for vertical gallium nitride (GaN) power diodes on foreign substrate [Yuhao Zhang et al, IEEE Electron Device Letters, published online 26 March 2018]. The researchers have developed a new platform for vertical GaN on silicon (Si) that creates a back-side trench, allowing a back contact to be made to the n-GaN layers.

The trench etching removes resistive buffer layers that have up to now mainly restricted GaN/Si power electronics to lateral or quasi-vertical structures with all contacts on the top side of epitaxial structures. The buffer layers are needed to bridge the lattice and thermal expansion mismatch between the foreign substrate and the GaN crystal structure. Fully vertical GaN power devices have generally been demonstrated on very expensive bulk or free-standing GaN substrates.

Vertical power devices are attractive because they push peak electric fields away from the surfaces and associated electron states that can cause premature breakdown. Vertical structures hence allow higher currents and voltages in more compact footprints. Also, lateral/quasi-vertical devices suffer from current crowding, which increases Joule heating.

Read more: Platform for fully vertical gallium nitride on silicon power devices, reposted […]

July 6th, 2018|General News Feed|

Semiconductor Engineering: Temporary Bonding: Enabling the Next Generation of Ultrathin Wafers

From Semiconductor Engineering:

Innovative materials are critical for maintaining integrity during advanced semiconductor manufacturing processes. Temporary bonding is being enabled by these new materials and is making a name for itself in the next generation of ultrathin wafer manufacturing.

Semiconductor wafers are being forced to become thinner as the push to shrink feature sizes and introduce full-scale 3D integration continues to grow.

While grinding wafers to less than 100 micrometers in thickness is a readily available process, moving to even thinner wafers (<50 µm) makes them exceedingly fragile. The stress of these extreme thinning processes and subsequent downstream metallization can cause additional stress on ultrathin wafers, contributing to warp or breakage.

The thin wafer handling process consists of temporarily mounting a device wafer to a carrier wafer with a polymeric bonding material system. This process is used to stabilize a wafer through harsh back-end processes while supporting the ultrathin device substrate. Two of the fastest growing release methods for debonding the wafer pairs are the laser and mechanical methods.

Source: Semiconductor Engineering: Temporary Bonding: Enabling the Next Generation of Ultrathin Wafers reposted by Silicon Valley Microelectronics, Inc. 

July 5th, 2018|General News Feed|

Semiconductor Engineering .:. Design Automation For Silicon Photonics: Pushing Research Into Production

From Semiconductor Engineering: 

Silicon photonics is a transformative technology that will have a major impact on system architectures in future IC design applications. Already a major solution for Datacom applications and emerging applications in sensing, design techniques in silicon photonics, with the ability to leverage CMOS technology to integrate large numbers of photonic components, are now being applied to enable optical computing. In almost all of these applications, however, an electrical interface is required, not just to provide modulation and detection signals, but to deliver real-time tuning to overcome manufacturing variability and temperature sensitivity inherent to silicon photonic components. In many cases, the supporting electrical connectivity and requisite I/O become dominant in the overall design process which includes floor-planning and physical implementation in photonic applications. Design tools, particularly tools for photonic circuit automation, need to be jointly aware of both the photonics and the electronics.

I’ve had a front row seat to development of design tools for photonics over the past seven years. It started with my involvement in a silicon photonics workshop in 2011. At that time, photonic workshops consisted of academics and researchers spending a week learning all the necessary details on every aspect of silicon photonic design, ranging […]

July 5th, 2018|General News Feed|

Monolithic indium phosphide on silicon growth for optoelectronics

From Semiconductor Today: 

Hong Kong University of Science and Technology (HKUST) has been advancing technologies for direct growth of indium phosphide (InP) on silicon (Si) substrate with a view to monolithic integration of optoelectronics on a low-cost platform.

In particular, professor Kei May Lau’s group at HKUST claims the first indium gallium arsenide/indium aluminium gallium arsenide (InGaAs/InAlGaAs multi-quantum-well (MQW) lasers directly grown on on-axis V-grooved (001) Si by metal-organic chemical vapor deposition (MOCVD) [Si Zhu et al, Optics Express, vol26, p14514, 2018]. Miscut silicon substrates are often used to grow III-V materials to avoid defects such as anti-phase boundaries.

Integration of lasers with on-axis silicon is desired for the interconnection of photonic integrated circuits and optical-fiber large-scale networking with the efficient, complex complementary metal-oxide-semiconductor (CMOS) electronics that powers today’s communications technologies. Monolithic integration, it is hoped, will reduce the costs arising from additional processing needed for wafer bonding, and also allow the use of larger-diameter substrates for economies of scale.

The V-groove Si was created by etching with potassium hydroxide solution through a silicon dioxide (SiO2) mask. The parallel stripes were made with a 130nm pitch. The silicon surface was prepared for MOCVD with 800°C thermal desorption of native oxide.

Read more: Monolithic indium […]

July 3rd, 2018|General News Feed|

TowerJazz announces RF SOI 65nm ramp in 300mm Japan fab

From Semiconductor Today:

Specialty foundry TowerJazz (which has fabrication plants at Tower Semiconductor Ltd in Migdal Haemek, Israel, and at its US subsidiaries Jazz Semiconductor Inc in Newport Beach, CA and TowerJazz Texas Inc in San Antonio, TX, and at TowerJazz Japan Ltd) has announced a ramp for its radio-frequency silicon-on-insulator (RF SOI) 65nm process in its 300mm fab in Uozu, Japan. TowerJazz has signed a contract with long-term partner SOITEC of Bernin, near Grenoble, France (which makes engineered substrates including SOI wafers) to guarantee a supply of tens of thousands of 300mm SOI silicon wafers, securing wafer prices for the next few years and ensuring supply to its customers, despite a very tight SOI wafer market.

“We are delighted to see the strong adoption of 300mm RF SOI through this large capacity and supply agreement with TowerJazz to augment our already significant 200mm RF SOI partnership,” says SOITEC’s CEO Paul Boudre. “TowerJazz was the first foundry to ramp our RFeSI products to high-volume production in 200mm,” he adds.

With what are claimed to be best-in-class metrics, TowerJazz’s 65nm RF SOI process enables the combination of low-insertion-loss and high-power-handling RF switches with options for high-performance low-noise amplifiers (LNAs) as well as digital […]

July 3rd, 2018|General News Feed|

44GHz silicon switches offer industry’s lowest insertion loss

From New Electronics: 
Analog Devices has released 44GHz single-pole, double-throw (SPDT) switches, the ADRF5024 and ADRF5025 in advanced Silicon-on-Insulator (SOI) technology.
The switches are broadband, with the ADRF5024 yielding flat frequency response from 100MHz to 44GHz, while the ADRF5025 from 9kHz to 44GHz, with repeatable characteristics better than 1.7dB insertion loss and 35dB channel to channel isolation.

Both parts support 27dBm power handling for both through and hot-switching conditions. The new switches come in a compact, 2.25mm x 2.25mm surface-mount-technology (SMT) compatible package, which will benefit radio frequency (RF) and microwave design experts, saving bias power, eliminating peripheral components and achieving higher integration in systems such as phased arrays, portable instrumentation, high resolution body scanners and next generation millimeter-wave communication infrastructure for emerging 5G and high-constellation satellite networks.

Read more: 44GHz silicon switches offer industry’s lowest insertion loss reposted by Silicon Valley Microelectronics, Inc. 

July 2nd, 2018|General News Feed|

Schottky diodes integrated in vertical gallium nitride transistors on silicon

From Semiconductor Today:

École Polytechnique Fédérale de Lausanne (EPFL) in Switzerland claims the first monolithic integration of vertical gallium nitride (GaN) metal-oxide-semiconductor field-effect transistors (MOSFETs) with freewheeling Schottky barrier diodes (SBD) grown on 6-inch silicon substrates by metal-organic chemical vapor deposition [Chao Liu et al, IEEE Electron Device Letters, published online 1 June 2018]. This builds on previous work [www.semiconductor-today.com/news_items/2018/jan/epfl_160118.shtml].

The researchers hope to find a lower-cost route to vertical GaN power devices than the very expensive processes based on high-price bulk or free-standing GaN substrates that are presently used in research. GaN substrates are used to avoid defects that reduce the critical electric field for breakdown. Vertical power devices should be able to handle higher voltages and currents than lateral architectures. The use of large-diameter silicon substrates should reduce costs, but growth of GaN on silicon tends to introduce many performance-killing defects.

Freewheeling diodes are used in power conversion applications to allow the flow of reverse-bias current in the off state, releasing energy stored in inductive elements. While the in-built body p-i-n diode of the EPFL structure does allow some current flow, the turn-on voltage is high, increasing losses during switching. SBDs have a much lower turn-on voltage, along with faster […]

June 29th, 2018|General News Feed|

Wafer demand for ‘More than Moore’ devices to grow by 10%, says Yole Développement

From New Electronics:
Wafer demand for ‘More than Moore’ (MtM) devices is expected to grow by 10% between 2017 and 2023, Yole Développement, the market research and strategy consulting company, reports.
Driven by the adoption of evermore electronic components in end products, the semiconductor industry is facing a new era, Yole claims. Device scaling and cost reduction will no longer continue on the path followed for the past few decades. Instead, semiconductor companies are seeking solutions that bridge the gap between cost and performance, whilst adding increased functionality through integration.

MtM devices (including MEMS & sensors, CMOS Image Sensors, power electronic, along with RF devices) represent this functional diversification of technologies, the report continues, combining performance, integration and cost – not limited to CMOS scaling. And their importance, Yole predicts, will become greater.

MtM devices reached almost 45million 8-inch eq wafers in 2017 and the demand is anticipated to reach more than 66m 8-inch eq wafers by 2023.

According to the report, 6-inch and 8-inch are forecast to represent more than 60% of MtM wafers’ total wafer consumption. However, Yole says 12-inch will represent the fastest growth between 2017 and 2023, with demand growing from 3.3m units to 7.5m by 2023. This is due […]

June 29th, 2018|General News Feed|

Thiol molecules drive gold atoms to form a forest of nanowires with useful properties

Adjustments to sulfur-containing molecules have enabled researchers to precisely control the growth of gold nanowires, which are potentially useful in various applications including biosensors and catalysis.

Ligand molecules are used to prevent nanostructures from growing too large, or forming unwanted shapes. Suzhu Yu of the A*STAR Singapore Institute of Manufacturing Technology and colleagues had previously found that sulfur-containing molecules called thiols, which bind to gold, could be used to grow very thin gold nanowires. Now they have investigated how exactly these thiols do their job, and shown that different types of thiols can fine-tune the shape and size of the nanowires.

The researchers attached gold particles a few nanometers wide to a wafer of silicon, and then dipped this assembly into a solution containing a gold compound, a thiol ligand, and a reducing agent that generated gold atoms. When they used a ligand called 4-mercaptobenzoic acid (4-MBA), the nanoparticles sprouted a forest of gold nanowires that were 6 nanometers across and about 1 micrometer long in 15 minutes (see image).

The ligand binds strongly to any exposed part of the gold nanowire, and interactions between ligand molecules keep them densely packed on the wire’s surface. This prevents gold atoms in solution from sticking to the sides of the […]

June 25th, 2018|General News Feed|

What Happened To Selective Deposition?

From Semiconductor Engineering:

For years, the industry has been working on an advanced technology called area-selective deposition for chip production at 5nm and beyond.

Area-selective deposition, an advanced self-aligned patterning technique, is still in R&D amid a slew of challenges with the technology. But the more advanced forms of technology are beginning to make some progress, possibly inching closer from the lab to the fab.

The concept behind the technology isn’t new. For decades, chipmakers have used deposition, a process that deposits a blanket of materials on a surface. In area-select deposition, though, the idea is to use atomic layer deposition (ALD) to deposit materials in exact places. Using a bottoms-up approach, area-selective deposition, sometimes called area-selective ALD, is used to pattern and self-align tiny features on devices. Potentially, it could reduce the number of lithography and etch steps in the manufacturing flow.

For years the industry has used various forms of selective deposition in the fab to deposit metal materials on metal surfaces in devices. But for the more advanced forms of area-selective deposition, a tool must deposit different combinations of material sets in chips, such as metals on dielectrics, dielectrics on metals and dielectrics on dielectrics.

That’s the big stumbling block in R&D and the fab. For these […]

June 25th, 2018|General News Feed|

High-material-yield halogen-free vapor phase epitaxy of gallium nitride

From Semiconductor Today:

Toyota Central R&D Labs Inc in Japan has been exploring ways to improve gallium use in growing gallium nitride (GaN) by vapor-phase epitaxy (VPE) on sapphire [Daisuke Nakamura and Taishi Kimura, Appl. Phys. Express, vol11, p065502, 2018]. Fast growth by hydride VPE typically incorporates less than 10% of the source gallium metal. The Toyota researchers comment: “This low yield is probably due to several factors, including a reverse reaction (etching) and the presence of a thick stagnant boundary layer on the seed surface (since the process is carried out under atmospheric pressure).”

The US Geological Survey estimates the global annual supply of gallium to be 300-400 tons, typically as a by-product of aluminium extraction, so this is clearly not a material to be wasted. It is further estimated that gallium constitutes 18-19 parts per million of the Earth’s crust.

And III-nitride applications such as short-wavelength light emission and and high-power and high-frequency electronics are not the only demands made on the chemical element. Gallium turns up in III-arsenide, III-phosphide and III-antimonide formations for longer-wavelength light and low-power-consumption and high-speed electronics. In the old days of the Soviet Union, gallium was favored as a neutrino detection material.

Toyota, as a car […]

June 25th, 2018|General News Feed|

Sounding out lasing in silicon

From Physics World:

Combining photonics and electronics would bring the advantages of speedy optical data transfer to the increasingly miniaturized world of electronics. Ideally photonics and electronics elements would be seamlessly integrated but many traditional photonics components are tricky to replicate in silicon, a fundamental challenge being a source of light on-chip. Now researchers at Yale University, Arizona University and the University of Texas at Austin show how this hurdle may be tackled using a silicon Brillouin laser.

When a material is strained, its refractive index changes due to “Brillouin scattering” from strain-induced deformations. In a crystal this strain may be due to acoustic vibrations in response to the electric field from an intense beam of light – stimulated Brillouin scattering. Put this scenario in a ring structure where the optical gain from stimulated scattering overcomes roundtrip loss and you have a Brillouin laser.

While the power and flexibility of Brillouin lasers has already attracted notice, as Peter Rakich, and Nils Otterstrom at Yale University and their co-authors point out in a report of their work, Brillouin interactions are markedly weak in conventional silicon photonic waveguides. The trick with this latest work was devising a silicon system with “unusually large Brillouin coupling”.

Narrowing in on Brillouin […]

June 19th, 2018|General News Feed|

Scientists demonstrate coherent coupling between a quantum dot and a donor atom in silicon

From phys.org:

Quantum computers could tackle problems that current supercomputers can’t. Quantum computers rely on quantum bits, or “qubits.” Current computers perform millions of calculations, one after the other. Qubit coupling allows quantum computers to perform them all at the same time. Qubits could store the data that add up to bank accounts and medical records. In an unusual twist, qubits represent data by the binary state of electron spins. Two systems existed to create qubits. Researchers successfully integrated the systems—donor atoms and quantum dots. The new qubits don’t let the spins, and hence the data, degrade. Specifically, the bits demonstrate coherent coupling of the electron spins. This hybrid approach, which has remained elusive until now, exploits the advantages of the two qubit systems.

For almost two decades, scientists have created theoretical proposals of such a hybrid qubit (donor qubit) architecture. Now, researchers have made an important step toward the practical realization of silicon qubits. Silicon matters. Why? It is the same material used today in our personal computers. The manufacturing process for qubits could fit within today’s manufacturing and computing technologies.

Qubits form the basis of quantum computation. Building a practical quantum computer demands two important features: the maintenance of coherent quantum states and the assembly […]

June 19th, 2018|General News Feed|

Robot vision makes solar cell manufacture more efficient

From phys.org:

“The price of solar-generated electricity continues to plummet, and the technology is taking over as the least expensive form of energy in more and more parts of the world,” says solar cell researcher John Atle Bones at SINTEF.

“We’re at an economic tipping point that favours solar cell technology,” he says. “Good illustrations of this from the USA include the Berkeley Energy Group/EDF Renewable Energy project, which recently shut down a coal mine and established a solar park on the same site. In California, the authorities have recently decided to introduce roof-based solar panel standards for new housing,” explains Bones.

Perfecting raw material selection

Price reductions in increasingly more popular solar panels are the result of developments in both technology and production methods – and it is exactly this technology and its raw materials that Bones and his colleagues are looking into. SINTEF researchers now intend to use robots to enhance the quality of the end product.

Perfecting the manufacture of so-called monocrystalline silicon (the material that forms the basis of a solar cell’s ability to generate electricity) has been preoccupying the research community at SINTEF for many years. Researchers have now focused their attention and, more to the point, that of their sensors towards […]

June 18th, 2018|General News Feed|

MXene’s tour de force

From phys.org:

Is there anything MXene materials can’t do?

Since the discovery of a large new family of two-dimensional materials by Drexel University researchers in 2011, continued exploration has revealed their exceptional ability to store energy, block electromagnetic interference, purify water and even ward off bacteria. And, as recent research now suggests, MXenes are also very durable—the strongest material of its kind, according to a new study in the journal Science Advances.

The finding, presented by researchers at Drexel and the University of Nebraska-Lincoln, shows that MXenes rate the highest among two-dimensional materials produced by solution processing—the standard method for making scalable, practically useful materials in the lab—in a measure called “elastic modulus.”

In a side-by-side comparison with graphene oxide or reduced graphene oxide, promising new materials that are already being used to add strength to rubber and polymers, a flake of the MXene titanium carbide proved to be about 50 percent stiffer.

This test of strength is performed by placing a single sheet of a material over a silicon wafer test surface with holes. Then a sharp tip of an atomic force microscope pokes the material, making an indentation. As this is happening, the probe is also measuring the force it takes to make the indentation—thus determining the strength and elastic modulus […]

June 18th, 2018|General News Feed|

Taiwan solar poly-Si wafer makers to ask for government help

From Digitimes:
Taiwan-based poly-Si solar wafer makers Green Energy Technology (GET), Gigastorage, Sino-American Silicon Products (SAS) and Danen Technology will jointly file a petition asking the government to adjust feed-in tariffs, according to industry sources.
The government offers a 6% markup in feed-in tariff rate for PV power stations or rooftop systems that adopt high-efficiency modules with VPC (voluntary product certification) from Bureau of Standards, Metrology and Inspection, the sources said. Consequently, PV modules made of mono-Si solar cells are adopted for 80% of PV power stations and rooftop systems, the sources noted.
However, 90% of mono-Si wafers used to make solar cells are imported from China, as AUO Crystal is the only Taiwan-based maker of solar mono-Si wafers, and all others Taiwan-based makers mostly or merely produce poly-Si wafers, together taking up over 80% of Taiwan’s solar wafer output, the sources indicated.
As a result, Taiwan-based solar poly-Si wafer makers have benefited little from the Taiwan government’s program boosting PV power generation since 2017, the sources noted.
In fact, demand for mono-Si wafers is high only in the China market where the government is encouraging adoption of high-efficiency PV modules for model power stations, the four makers argued.
Except China, only 20-30% of global […]

June 14th, 2018|General News Feed|

New laser makes silicon ‘sing’

From phys.org:

Yale scientists have created a new type of silicon laser that uses sounds waves to amplify light. A study about the discovery appears June 8 in the online edition of the journal Science.

In recent years, there has been increasing interest in translating optical technologies—such as fiber optics and free-space lasers—into tiny optical or “photonic” integrated circuits. Using light rather than electricity for integrated circuits permits sending and processing information at speeds that would be impossible with conventional electronics. Researchers say silicon photonics—optical circuits based on silicon chips—are one of the leading platforms for such technologies, thanks to their compatibility with existing microelectronics.

“We’ve seen an explosion of growth in silicon photonic technologies the past few of years,” said Peter Rakich, an associate professor of applied physics at Yale who led the research. “Not only are we beginning to see these technologies enter commercial products that help our data centers run flawlessly, we also are discovering new photonic devices and technologies that could be transformative for everything from biosensing to quantum information on a chip. It’s really an exciting time for the field.”

The researchers said this rapid growth has created a pressing need for new silicon lasers to power the new circuits—a problem that has […]

June 14th, 2018|General News Feed|

Gallium nitride tunnel junctions from pure MOCVD process for VCSELs

From phys.org:

University of California Santa Barbara (UCSB) in the USA claims the first demonstration of a III-nitride semiconductor vertical-cavity surface-emitting laser (VCSEL) with a tunnel junction (TJ) on the p-side using only metal-organic chemical vapor deposition (MOCVD) material growth [SeungGeun Lee et al, Appl. Phys. Express, vol11, p062703, 2018].

Tunnel junctions are seen as an alternative to indium tin oxide (ITO) as a current-spreading material on the p-side of light-emitting III-nitride devices. Indium tin oxide increases laser threshold currents and absorbs light, reducing efficiency.

VCSELs offer desirable characteristics such as compactness, low thresholds, large modulation bandwidth, narrow linewidths, and circular beam patterns.

Tunnel junctions of heavily doped p- and n-type material have been created before for VCSELs, but the UCSB team reports that these have used hybrid growth processes involving MOCVD and molecular beam epitaxy (MBE). An MOCVD-only process is preferred since MBE is performed at lower temperatures, leading to higher defect density and impurity incorporation. Defects and impurities increase non-radiative recombination, reducing efficiency.

The VCSEL epitaxial material consisted of layers grown by MOCVD on bulk m-plane gallium nitride (GaN), miscut by -1° in the c-direction. Growth was carried out in two steps to allow activation of the buried p-type layers. Such layers […]

June 14th, 2018|General News Feed|

Robot and machine vision aid silicon solar cell manufacture

From Laser Focus World:

Perfecting the manufacture of monocrystalline silicon (the material that forms the basis of most photovoltaic panels) has been preoccupying the research community at SINTEF (Trondheim, Norway) for many years. The researchers have now focused their attention and, more to the point, that of their sensors on the important quartz crucible that plays one of the key roles in the manufacture of solar cells. They have developed an optical-sensor-laden robot to better inspect these crucibles.

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Quartz crucible characteristics
These quartz crucibles are between 50 and 70 cm in diameter with walls about 1 cm thick. The quality of a crucible is very important. If it is inadequate, the end product will be unusable. The crucible is built up of different quartz layers that perform a variety of functions during the manufacturing process. It acts as a container used in the furnaces that melt silicon prior to the production of monocrystalline silicon.

As part of this process, a seed silicon crystal is dipped into the molten silicon and a large monocrystalline […]

June 13th, 2018|General News Feed|

Does nanoconfinement affect the interaction between two materials placed in contact?

From phys.org:

A research team from the Université libre de Bruxelles shows that it is possible to estimate how nanoconfinement affects the number of contacts formed by two materials placed in intimate contact and, hence, the interfacial interactions.

They considered wafers of silicon, as those largely used in microelectronics, coated by thin polymer layers of different thickness. The currently used approximate methods predict that the interaction between the two materials does not depend on the thickness of the polymer layer. On the contrary, the team of the Université libre de Bruxelles (ULB) lead by Simone Napolitano (Polymer and Soft Matter Dynamics – Faculty of Sciences), showed that size does matter. Molecules at the interface of thinner films form less contacts with the silicon wafer, because the vdW forces (van der Waals (vdW) forces, that depend on the dimension of the objects involved) are weaker. The method used permitted to verify a striking correlation between the intensity of the vdW forces and the number of contacts.

This result shows that the current way we think at interfaces is not valid. In addition to the huge impact at the level of fundamental science, the results of the researchers of ULB could be exploited on a large number of […]

June 13th, 2018|General News Feed|

Silicon provides a way to control quantum bits for faster algorithms

From New Electronics:
A discovery of an enhanced spin-orbit interaction in silicon could be used to manipulate quantum bits. The hope is this could lead to faster and longer-lived information processing via quantum computing.
The researchers from Purdue University, the Technological University of Delft, Netherlands and the University of Wisconsin-Madison explain that this finding can be used to control qubits using electric fields, without the need for any artificial agents.

“Qubits encoded in the spins of electrons are especially long-lived in silicon, but they are difficult to control by electric fields. Spin-orbit interaction is an important knob for the design of qubits that was thought to be small in this material, traditionally,” explains Assistant Professor Rajib Rahman, research assistant professor at Purdue.

The researchers found more prominent spin-orbit interaction than usual at the surface of silicon where qubits are located in the form of so-called quantum dots – electrons confined in three dimensions. Assist Prof. Rahman’s lab identified that this spin-orbit interaction is anisotropic in nature – meaning that it is dependent on the angle of an external magnetic field – and strongly affected by atomic details of the surface.

“This anisotropy can be employed to either enhance or minimise the strength of the […]

June 12th, 2018|General News Feed|

Tiny defects in semiconductors created ‘speed bumps’ for electrons—researchers cleared the path

From phys.org:

UCLA scientists and engineers have developed a new process for assembling semiconductor devices. The advance could lead to much more energy-efficient transistors for electronics and computer chips, diodes for solar cells and light-emitting diodes, and other semiconductor-based devices.

A paper about the research was published in Nature. The study was led by Xiangfeng Duan, professor of chemistry and biochemistry in the UCLA College, and Yu Huang, professor of materials science and engineering at the UCLA Samueli School of Engineering. The lead author is Yuan Liu, a UCLA postdoctoral fellow.

Their method joins a semiconductor layer and a metal electrode layer without the atomic-level defects that typically occur when other processes are used to build semiconductor-based devices. Even though those defects are minuscule, they can trap electrons traveling between the semiconductor and the adjacent metal electrodes, which makes the devices less efficient than they could be. The electrodes in semiconductor-based devices are what enable electrons to travel to and from the semiconductor; the electrons can carry computing information or energy to power a device.

Generally, metal electrodes in semiconductor devices are built using a process called physical vapor deposition. In this process, metallic materials are vaporized into atoms or atomic clusters that then condense onto the semiconductor, […]

June 12th, 2018|General News Feed|

Solar cells combining silicon with perovskite have achieved record efficiency of 25.2 percent

From Tech Xplore:

In the field of photovoltaic technologies, silicon-based solar cells make up 90 percent of the market. In terms of cost, stability and efficiency (20-22 percent for a typical solar cell on the market), they are well ahead of the competition.

However, after decades of research and investment, silicon-based solar cells are now close to their maximum theoretical efficiency. As a result, new concepts are required to achieve a long-term reduction in solar electricity prices and allow photovoltaic technology to become a more widely adopted way of generating power.

One solution is to place two different types of solar cells on top of each other to maximize the conversion of light rays into electrical power. These “double-junction” cells are being widely researched in the scientific community, but are expensive to make. Now, research teams in Neuchâtel—from EPFL’s Photovoltaics Laboratory and the CSEM PV-center—have developed an economically competitive solution. They have integrated a perovskite cell directly on top of a standard silicon-based cell, obtaining a record efficiency of 25.2 percent. Their production method is promising, because it would add only a few extra steps to the current silicon-cell production process, and the cost would be reasonable. Their research has been published in Nature Materials.

Perovskite-on-silicon: a nanometric sandwich

Perovskite’s unique […]

June 12th, 2018|General News Feed|