Silicon Industry News

Latest news from the semiconductor industry

New Power Concerns At 10/7nm

From Semiconductor Engineering:

As chip sizes and complexity continues to grow exponentially at 7nm and below, managing power is becoming much more difficult.

There are a number of factors that come into play at advanced nodes, including more and different types of processors, more chip-package decisions, and more susceptibility to noise of all sorts due to thinner insulation layers and wires. The result is that engineers now need to consider a slew of thermal, packaging and electromagnetic issues that were never serious concerns at previous nodes.

At a high level, these factors dramatically increase the importance of analyzing power from a system level, across multiple different operating scenarios and process corners.

“What is needed is the ability to analyze this large power data and use it to enable timely decisions that can impact the design process,” said Arti Dwivedi, principal technical product manager at ANSYS. “This stresses the need for data analytics-based power solutions with elastic compute and big data architectures.”

This requires more than just tooling, though. “At advanced nodes, low power and high performance designs is a big challenge not just for design styles but also for design flows,” said Jerry Zhao, product management director in the Digital & Signoff Group at […]

October 16th, 2017|General News Feed|

Demand for 12-inch silicon wafers to surge in China

From Digitimes:

Demand for blank 12-inch silicon wafers is set to increase to 1.1-1.3 million pieces per month in China in 2018, up from the current 500,000 units, according to local media.

With China pushing for self-sufficiency in semiconductors, the country is aware of its heavy reliance on imported 12-inch silicon wafers. As domestic demand for 12-inch silicon wafers is set to hike, China will have its first homegrown 12-inch silicon wafer supplier ready to enter volume production at the end of 2017, according to the local media reports.

Shanghai Xinsheng Semiconductor Technology was founded by Richard Zhang, founder and former CEO of China’s largest pure-play foundry Semiconductor Manufacturing International (SMIC). Shanghai Xinsheng is scheduled to come online at the end of 2017 with monthly capacity of 150,000 12-inch wafers in the first phase, and the monthly capacity will double to 300,000 units by 2020, the reports said.

Demand for blank 8-inch silicon wafers is also expected to surge reaching 7.5-8 million units in 2020, up from the current 800,000, the reports indicated.

There are already companies based in China engaged in the production of 8-inch silicon wafer materials, including QL Electronics, Kunshan Sino Silicon Technology, Grinm Semiconductor Materials, Hebei Poshing Electronics Technology, Nanjing […]

October 16th, 2017|General News Feed|

Low-threshold indium arsenide quantum dot laser diodes on silicon

From Semiconductor Today:

University of California Santa Barbara (UCSB) in the USA claims record low threshold currents for indium arsenide (InAs) quantum dot (QD) laser diodes (LDs) grown on silicon (Si) [Daehwan Jung et al, Appl. Phys. Lett., vol111, p122107, 2017]. The team says further that the 6.7mA threshold achieved is the lowest for any kind of Fabry-Perot laser grown on silicon. The use of QDs ameliorates problems arising from threading dislocations in lattice-mismatched crystal structures on silicon.

Combined with silicon photonics (waveguides, etc), the researchers see potential for a monolithically integrated, efficient light source to power high-performance, chip-scale optical interconnects to meet growing demand for data bandwidth.

The researchers used on-axis (001) gallium phopshide (GaP) on Si substrates, which are available commercially from NAsPIII/V GmbH in diameters up to 300mm. Although miscut off-axis silicon enables gallium arsenide (GaAs) to be grown directly without anti-phase domains, on-axis substrates are preferred for manufacturing in standard CMOS processing foundries. GaP has been found to terminate anti-phase domains within 40nm of the silicon interface.

Figure 1: (a) Cross-sectional schematic of InAs QD laser structure grown on GaP/Si substrate. (b) Electron channeling contrast images showing threading dislocations before and (c) after optimization of GaAs/GaP/Si template.

Solid-source molecular beam […]

October 16th, 2017|General News Feed|

How the semiconductor industry is taking charge of its transformation

From McKinsey & Company:

Semiconductors are the unsung heroes of technology, providing high-speed processing power for computers, flat-screen displays, smartphones, and other electronic devices.

But while semiconductor revenues are hitting record levels, recent geographic and product shifts are upending long-standing business plans. Moreover, R&D budgets are rising by about 6 percent annually because of new technological and business challenges, such as increased complexity in coding, testing, and verification.

Three developments in the semiconductor industry—the evolving demand for automotive chips, the availability of new productivity tools, and the growth of China as a revenue source—provide opportunities to increase performance.

Changing in tandem: Opportunities in the automotive sector

If you walked into an electronics convention today, you might see hundreds of exhibits from automotive OEMs. Their displays typically focus on new car features that rely on sophisticated electronics, such as mapping applications and automatic-braking systems. This emphasis on innovation has helped increase revenues for automotive semiconductors from about $7 billion in 1996 to almost $30 billion in 2015 (Exhibit 1). Automotive chips now account for about 8 percent of total semiconductor sales, and current projections suggest that they will see about 6 percent annual growth through 2020—higher than the 3 to 4 percent growth predicted for the […]

October 12th, 2017|General News Feed|

Injecting electrons jolts 2-D structure into new atomic pattern


Schematic shows the configuration for structural phase transition on a molybdenum ditelluride monolayer (MoTe2, shown as yellow and blue spheres), which is anchored by a metal electrodes (top gate and ground). The ionic liquid covering the monolayer and electrodes enables a high density of electrons to populate the monolayer, leading to changes in the structural lattice from a hexagonal (2H) to monoclinic (1T’) pattern. Credit: Ying Wang/Berkeley Lab

The same electrostatic charge that can make hair stand on end and attach balloons to clothing could be an efficient way to drive atomically thin electronic memory devices of the future, according to a new study led by researchers at the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab).

In a study published today in the journal Nature, scientists have found a way to reversibly change the atomic structure of a 2-D material by injecting, or “doping,” it with electrons. The process uses far less energy than current methods for changing the configuration of a material’s structure.

“We show, for the first time, that it is possible to inject electrons to drive structural phase changes in materials,” said study principal investigator Xiang Zhang, senior faculty scientist at Berkeley Lab’s Materials Sciences Division […]

October 12th, 2017|General News Feed|

The Many Flavors of SOI

From EE Journal:

At this year’s Semicon West show, Soitec made a presentation summarizing the state of the union with respect to silicon-on-insulator (SOI) technology. We’ve looked at FD-SOI a couple of times, particularly with respect to GLOBALFOUNDRIES’ implementations at 22 and 12 nm. But today we’re going to look more generically at the technology – and the fact that there are various extant flavors of SOI and that that will continue. (We’ll return to GLOBALFOUNDRIES in a future piece.)

The major take-away for those of us more focused on logic design is that FD-SOI is a recent addition to the SOI family (relatively speaking). Turns out that RF-SOI is, at present, about 60% of SOI sales. Who knew! And Power SOI is another 20%.

The non-FD-SOI versions (also known as partially-depleted SOI, or PD-SOI) have different design constraints, and so they are built differently to solve problems within their target applications. We’ll work through these varieties here, starting with a review of what makes them SOI.

Silicon on Something

I remember in school being vaguely aware of something called Silicon on Sapphire, or SOS – which still survives with Peregrine Semiconductor. Sapphire is an insulator, and so this would be a specific case […]

October 12th, 2017|General News Feed|

NVIDIA unveils next-generation platform for fully autonomous cars

Silicon Valley graphics chipmaker NVIDIA unveiled on Tuesday the first computer chips for developing fully autonomous vehicles and said it had more than 25 customers working to build a new class of driverless cars, robotaxis and long-haul trucks.

FILE PHOTO: The logo of Nvidia Corporation is seen during the annual Computex computer exhibition in Taipei, Taiwan May 30, 2017. REUTERS/Tyrone Siu/File Photo

Deutsche Post DHL Group, the world’s largest mail and logistics company, and ZF [ZFF.UL], a top automotive parts supplier, plan to deploy a fleet of autonomous delivery trucks based on the new chips, starting in 2019, NVIDIA said.

The third generation of NVIDIA’s Drive PX automotive line, code-named Pegasus, is a multi-chip platform the size of car license plates with datacenter-class processing power.

Pegasus can handle 320 trillion operations per second, representing roughly a 13-fold increase over the calculating power of the current PX 2 line.

A single NVIDIA Xavier-class processor can be used for level 3 semi-autonomous driving, while a combination of multiple mobile and graphics processors would run level 5 full-scale driverless cars, the company said.

A level 5 vehicle is capable of navigating roads without any driver input and in its purest form would have no steering wheel or brakes. […]

October 11th, 2017|General News Feed|

Researchers fabricate 3-D silicon structures with a focused infrared laser


Physicist Richard Feynman once gave a lecture titled “There is plenty of room at the bottom.” This lecture is often quoted to highlight the successes of modern micro- and nano-fabrication techniques, and the value of available space that comes with advances in miniaturization. In this respect, silicon, the bedrock of modern computers, mobile communications, and photonic devices, has proven to be extremely capable. These advances are usually described in terms of Moore’s law. However, modern processors are essentially stacks of planar structures. In this sense, silicon microelectronics and photonics are still 2-D.

Now, a diverse team of scientists centered at Bilkent University and Middle East Technical University (both in Ankara, Turkey) have found a way to pack laser-written structures deep inside silicon chips. In the latest issue of Nature Photonics, the researchers describe their novel approach, which uses a focused infrared laser beam to create 1-μm-resolution building blocks in a sliver of silicon. For the first time, the researchers demonstrate arbitrary 3-D fabrication inside silicon, without structures above or below.

Then, the researchers converted these complex 3-D architectures into functional optical devices such as lenses, waveguides, holograms and other optical elements. “We achieved this by exploiting dynamics arising from nonlinear […]

October 11th, 2017|General News Feed|

Indium gallium nitride quantum dot microcavity light emission

From Semiconductor Today:

Researchers in China have developed tunable indium gallium nitride (InGaN) quantum dot (QD) microcavity (MC) visible light emitters with a 129nm wavelength range from yellow-green to violet from electrical pumping [Yang Mei et al, Appl. Phys. Lett., vol111, p121107, 2017]. The device included distributed Bragg reflectors (DBR) forming the Fabry-Perot cavity.

The team from Xiamen University, East China Normal University, Suzhou Institute of Nano-tech and Nano-bionics (SINANO) and China Academy of Engineering Physics comment: “As the first electrically driven III-V nitride semiconductor based tunable MC light emitter with a tuning range of 129nm, the device is promising for applications such as in wide-gamut compact displays and projectors.”

The researchers also believe that biomedical, mood-lighting, and broad-band communication applications could benefit from monolithic broadband and wavelength tunable light sources.

The semiconductor material (Table 1) was grown on (0001) c-plane sapphire using metal-organic chemical vapor deposition (MOCVD). The QD layer was grown in Stranski-Krastanov mode at 670°C for high indium content. The subsequent GaN barrier was applied in two steps: at 670°C as a 2nm-thick matrix for the QDs to inhibit indium desorption, and then ramped up to 850°C for the 8nm barrier material.

Table 1: Detailed structure of epitaxial wafer.

Layer structure
Thickness (nm)

Flat […]

October 11th, 2017|General News Feed|

Uncertainty has become the new normal as the era of Moore’s law draws to a close

From South China Morning Post:

Last Tuesday, the world’s biggest chip maker, Intel, whose brand is synonymous with personal computers and laptops, announced that its former chief executive Paul Otelini had passed away in his sleep at the age of 66. As the fifth chief executive of the company, Otelini presided over the period of largest growth in the company, raising the annual revenue from US$34 billion to US$53 billion in 2012. In fact, more money was made under his eight year reign than in the previous 37 years of Intel’s existence. No other company can fire out a better and faster microprocessor, the engine that spurs into motion when you turn your computer on.

But the dominance of Intel is as much about its inventiveness as its ability to predict product advancement. No other industry manages to engineer miracles with such absolute transparency. We tend to perceive innovation as something uncertain, and progress made by scientists can be slow at times. Yet, that’s not how Intel behaves. It’s clockwork; it’s anything but ambiguous.

In 1965, Intel co-founder Gordon Moore made a bold prediction about the exponential growth of computing power. From the vacuum tube to the discrete transistor to the integrated […]

October 10th, 2017|General News Feed|

Watch: First Millimeter-Wave Non-Reciprocal Circulator Implemented on a Silicon Chip

From Electronics360:

Columbia University engineers report development of the first magnet-free non-reciprocal circulator on a silicon chip that operates at millimeter-wave frequencies (frequencies near and above 30 GHz).

Signal transmission in most devices is characterized by reciprocity — signals travel in the same manner in forward and reverse directions. Circulators and other nonreciprocal devices allow forward and reverse signals to traverse different paths and therefore be separated. Nonreciprocal devices have been built from special magnetic materials that make them bulky, expensive and not suitable for consumer wireless electronics.

Chip microphotograph of the 25GHz fully-integrated non-reciprocal passive magnetic-free 45nm SOI CMOS circulator based on spatio-temporal conductivity modulation. (Credit: Tolga Dinc/Columbia Engineering)

The new mode for nonreciprocal transmission of waves is based on synchronized high-speed transistor switches that route forward and reverse waves differently. Think of two trains approaching each other at super-high speeds that are detoured at the last moment to avoid colliding.

The advance enables circulators to be built in conventional semiconductor chips and operate at millimeter-wave frequencies, supporting full-duplex or two-way wireless. Virtually all electronic devices currently operate in half-duplex mode at lower radio-frequencies (below 6 GHz) and devices are rapidly running out of bandwidth. Full-duplex communications, in which a transmitter and a […]

October 10th, 2017|General News Feed|

Researchers image perfectly smooth side-surfaces of 3-D silicon crystals with a scanning tunneling microscope

From research collaboration between Osaka University and the Nara Institute of Science and Technology for the first time used scanning tunneling microscopy (STM) to create images of atomically flat side-surfaces of 3-D silicon crystals. This work helps semiconductor manufacturers continue to innovate while producing smaller, faster, and more energy-efficient computer chips for computers and smartphones.

Our computers and smartphones each are loaded with millions of tiny transistors. The processing speed of these devices has increased dramatically over time as the number of transistors that can fit on a single computer chip continues to increase. Based on Moore’s Law, the number of transistors per chip will double about every 2 years, and in this area it seems to be holding up. To keep up this pace of rapid innovation, computer manufacturers are continually on the lookout for new methods to make each transistor ever smaller.

Figure.3. Spatial-derivative STM images with 200×200 nm^2 at Vs = +1.5 V. Flat terraces become brighter and edges darker. The downstairs direction runs from left ((110) top-surface) to right ((-1-10) back-surface). Credit: Osaka University

Current microprocessors are made by adding patterns of circuits to flat silicon wafers. A novel way to cram more transistors in the same […]

October 10th, 2017|General News Feed|

Superconductivity found in thin films of TiO2


Many of us are familiar with titanium dioxide (TiO2), a whitener commonly used in sunscreens and paints such as the white lines seen on tennis courts. Less well known are other higher titanium oxides—those with a higher number of titanium and oxygen atoms than TiO—that are now the subject of intensifying research due to their potential use in next-generation electronic devices.

Now, researchers at Tokyo Tech have reported superconductivity in two kinds of higher titanium oxides prepared in the form of ultrathin films. With a thickness of around 120 nanometers, these materials reveal properties that are only just beginning to be explored.

“We succeeded in growing thin films of Ti4O7 and γ-Ti3O5 for the first time,” says Kohei Yoshimatsu, lead author of the paper published in Scientific Reports.

Until now, the two materials had only been studied in bulk form, in which they behave as insulators—the opposite of conductors. The formation of electrically conductive thin films is therefore seen as a big advance for fundamental physics.

The researchers found that the superconducting transition temperature reached 3.0 K for Ti4O7 and 7.1 K for γ-Ti3O5. Achieving 7.1 K even in simple metal oxides is “an amazing result”, says Yoshimatsu, as “it represents one […]

October 6th, 2017|General News Feed|

Defect Engineering in Weyl Semimetals

From AZO Materials:

Interest in topological insulators has exploded since graphene first made its name in the scientific community. One area which has gained a lot of interest is that of Weyl semimetals (WSMs), due to their unique band and transport properties.

A team of Researchers from China have introduced defects into tungsten telluride (WTe2) samples using gallium ions to study the effects that defects have on the properties and electronic structure of the material.

Weyl semimetals were first implemented into the tantalum arsenide (TaAs) family and have since grown in popularity because of their unique band structure and transport properties.

Many theoretical forms of Weyl semimetals, such as Weyl point, Weyl cone, Fermi arc and chirality anomaly, have come to experimental fruition in recent years and the area is still expanding.

A recent discovery in the Weyl family is type II Weyl semimetals. These have been confirmed in WTe2, MoTe2 and MoxW1-xTe2 compounds and are now known to feature Weyl cones which appear at contact points between holes and electrons.

Of all the type II Weyl Semimetals, WTe2 has gathered the most attention and many of the properties in pure WTe2 have been deduced experimentally using a series of spectroscopy techniques.

One area which is […]

October 6th, 2017|General News Feed|

Step-flow growth of green-emitting indium gallium nitride quantum wells

From Semiconductor Today:

University of Chinese Academy of Sciences has improved green light internal quantum efficiency from indium gallium nitride (InGaN) quantum wells (QWs) by increasing the miscut angle of the gallium nitride template to encourage step-flow growth [Aiqin Tian et al, Appl. Phys. Lett., vol111, p112102, 2017].

The researchers claim that step-flow QWs have not been achieved up to now for green light-emitting InGaN. Instead, green InGaN QWs tend to be formed from two-dimensional (2D) island growth.

The team was partly motivated by the desire for improved green light performance in laser diodes (LDs) for picoprojectors and displays. Indeed, the work included the fabrication of laser diodes with reduced threshold current.

The InGaN QWs were grown on a 2μm n-GaN buffer by low-pressure metal-organic chemical vapor deposition. The QWs consisted of 2.5nm InGaN layers grown at 688°C, while the separating GaN barriers were grown at 850°C.Ammonia was used for the nitrogen precursor. The gallium component came from trimethyl-gallium for the barriers and buffer and triethyl-gallium for the wells. The indium source was trimethyl-indium.

High-quality step-flow growth for 27%-indium-content green QWs was encouraged by increasing the miscut angle of the GaN/sapphire template from 0.20° to 0.48°. This reduced the step terrace width from ~80n […]

October 6th, 2017|General News Feed|

TSMC 3nm fab plan to create huge biz opportunities for supply chains

The decision made by Taiwan Semiconductor Manufacturing (TSMC) to build its 3nm wafer fab in the Southern Taiwan Science Park has won acclaims from both member firms of the TSMC Grand Alliance and Taiwan’s IC packaging and testing firms, as the clustering effect triggered by the leading foundry house will continue generating huge business opportunities for equipment and materials suppliers and even outsourced semiconductor assembly and test (OSAT) firms.

The ensuing geographic proximity will be conducive to the development of back-end companies. For instance, as a member of the Grand Alliance, Chunghwa Precision Test Tech (CHPT) said that the company will invest more in talent cultivation and R&D to supply more advanced wafer probe cards. The firm’s general manager SK Huang said that after entering the 7/5/3 nm nodes, wafer fabrication requires higher costs and therefore more precision wafer probing will be badly needed. CHPT has now maintained offices in Taoyuan, Hsinchu and Kaohsiung to provide quick services to customers.

IC packaging and testing industry insiders said that TSMC is likely to continue using its in-house InFO (integrated fan-out) or CoWoS (chip on wafer on substrate) advanced technologies to package application processor chips for Apple’s iPhones or AI (artificial intelligence) chips […]

October 5th, 2017|General News Feed|

Terahertz nanoprobing for ultrafast surface dynamics measurements of bulk semiconductors

From Nanowerk News:

(Nanowerk News) Researchers have demonstrated ultrafast surface dynamics measurements of bulk semiconductors (SI-InP and SI-GaAs) using a terahertz (THz) nanoprobing method.

The Korean research team has reported their findings in Nano Letters (“Terahertz Nanoprobing of Semiconductor Surface Dynamics”).

Surface carrier dynamics in semiconductor materials are related to the band structure of the materials, ion-doping, and surface states, which can be drastically different from its bulk counterpart. Understandably, such carrier dynamics and surface properties are crucial for the performance of semiconductor-based optoelectronic and photovoltaic devices.

Despite their importance, direct measurements of the surface properties have been hindered by technical difficulties.


(a) A schematic representation of photoinduced carriers around nanopatterns on a semiconductor. As closer to the surface, the recombination time of carriers (electrons in blue and holes in red) is getting faster as described. The faster carrier dynamics near the extreme surface then can be captured by a tightly localized THz probe. (b) Carrier dynamics of bare and nanopatterned InP (top) and GaAs (bottom) measured from optical pump THz-probe spectroscopy. The gap sizes is 150 and 500 nm for InP and GaAs, respectively. Once the patterns are etched, the carrier recombination processes are completely recovered to the characteristics of bare samples. (© […]

October 5th, 2017|General News Feed|

What’s Next for the IoT?

From Semiconductor Engineering:

The Internet of Things continues to evolve, attempting to overcome its poor reputation for cybersecurity and making the case for wider adoption, especially by enterprises. Consumer IoT, largely represented in smart-home automation, remains a market being targeted by Amazon, Apple, Google, LG Electronics, Samsung Electronics, and other technology titans.

The big bucks are in Industrial IoT, though. That market has attracted AT&T, IBM, Microsoft, Oracle, Verizon Communications, and hundreds of startups. Some of those startups, such as C3 IoT and Uptake Technologies, have achieved “unicorn” status and attracted significant investments. The Chicago-based Uptake is a shining example of the industry transition from platform-as-a-service business models to software-as-a-service.

Many of the savvier startups are adding artificial intelligence and machine learning to their technology portfolios, complementing their IoT focus.

Ron Lowman, strategic marketing manager for IoT at Synopsys, points to the development of the Industrial IoT, machine learning, audio technology, and voice recognition/processing as important trends in IoT. He notes that connectivity is the big trend in the IoT market and in IoT technology.

“Industrial IoT has been a big conversation piece,” he says. “It’s really moving out of what was smart home last year. There’s now a lot more smart farming, smart industry, […]

October 5th, 2017|General News Feed|

Jayant Baliga’s Quest to Make Silicon-Carbide Power Electronics Succeed

From IEEE:

When Jayant Baliga invented the insulated gate bipolar transistor in the 1970s—something for which he won the 2014 IEEE Medal of Honor—it went from prototype to commercial product in about a year and a half. His quest to make silicon carbide a key material for power electronics has taken decades longer. But thanks to some recent innovations, he’s almost there. Two are new devices, impossible to make in silicon, and the third is a foundry process that will finally make SiC devices cost-competitive with silicon.

Silicon carbide is such desirable stuff because it has a much wider bandgap than silicon. That is, it takes more energy—about 3 times as much—for its electrons to go from being bound to their atoms to flowing as current than it does in silicon. So, devices made from SiC can be smaller and yet handle higher voltages more efficiently. Silicon power electronics tend to lose 10 percent of their power, while silicon carbide loses just 7 percent. And the higher frequency operations means the passive components attached to them—inductors and capacitors—can be smaller.

The problem has always been silicon carbide’s price relative to silicon. Right now it’s about five times as expensive. “Our goal is to get […]

October 4th, 2017|General News Feed|

Reducing costs for gallium arsenide Schottky diode fabrication

From Semiconductor Today:

The University of Sherbrooke and École de Technologie Supérieure in Canada have developed a gallium arsenide (GaAs) Schottky diode fabrication technique aimed at low-cost sub-millimeter wave performance [Sarvenaz Jenabi et al, Semicond. Sci. Technol., vol32, p105006, 2017]. The researchers used photolithography rather than the more expensive electron-beam patterning that is often used. Also, the number of metallization steps was reduced from five to two, reducing lithography alignment complexities from eight steps to five.

The team points out that, while Schottky diodes are key elements in electronic circuits, their fabrication becomes more and more challenging at high frequencies due to the small size of the device and high sensitivity to parasitic elements.

Figure 1: Schematic side view of fabricated diode.

A significant reduction in parasitic capacitance was achieved by the use of air-bridge connections to the transmission lines (Figure 1). The researchers report: “The proposed fabrication method with large stand-off height for the air-bridge, wide and deep trenches has reduced the parasitic capacitance to less than 0.7fF. We expect a practical cut-off frequency of 0.85 and 1.4THz for these diodes.”

The researchers used a GaAs wafer designed for heterojunction bipolar transistors, etching away unwanted layers to leave a lightly doped n-GaAs layer […]

October 4th, 2017|General News Feed|

‘New era’ in solar energy fuelling growth in renewables: IEA


The renewable energy sector is growing faster than expected, driven largely by a “new era” in solar power and strong expansion in China, the International Energy Agency said on Wednesday.

“What we are witnessing is the birth of a new era in solar PV (photovoltaic),” IEA executive director, Fatih Birol, said in a new report.

“We expect that solar PV capacity growth will be higher than any other renewable technology through 2022.”

The IEA calculated that new solar PV capacity grew by 50 percent last year, with China accounting for almost half of the global expansion.

“For the first time, solar PV additions rose faster than any other fuel, surpassing the net growth in coal,” the agency said.

And boosted by that expansion in the solar sector, “renewables will continue to have a strong growth in coming years. By 2022, renewable electricity capacity should increase by 43 percent,” the report said.

Renewables accounted for almost two-thirds of net new power capacity around the world last year, the IEA calculated.

“We see renewables growing by about 1,000 GW (gigawatt) by 2022, which equals about half of the current global capacity in coal power, which took 80 years to build,” executive director Birol said.

The upward revision in […]

October 4th, 2017|General News Feed|

New SoC Improves Sleep Mode Current Consumption and Battery Life in Devices

From Electronics 360:

Mouser Electronics is now stocking the BlueNRG-2 system-on-chip (SoC) from STMicroelectronics (ST). The BlueNRG-2 SoC is a power-efficient programmable processor with ultra-low-power features, high RF signal strength and generous on-chip memory for Bluetooth® low energy software and application code. The BlueNRG-2 is a Bluetooth, 4.2-compliant and Bluetooth 5.0-certified. This ensures interoperability with the latest generation of smartphones and supports enhanced features, like state-of-the-art security, privacy and extended packet length for faster data transfer.

ST’s BlueNRG-2 wireless SoC offers the same RF performance as the BlueNRG radio and improves sleep mode current consumption for longer applications and battery lifetime. The SoC has a 32-bit Arm® Cortex®-M0 processor and a Bluetooth low energy radio for energy efficiency and radio performance. The BlueNRG-2 includes 256 kBytes of on-chip flash memory which allows designers to embed the Bluetooth low energy stack and the application code; 24 kBytes of static RAM with retention (in two 12-kBytes of static RAM with retention; and SPI, UART I²C standard communication interface peripherals.

The device benefits from an ultra-low-power design, including support for fast wake-up and sleep transitions and a standby current of 500 nA. The RF-output power is boosted to +8 dBm to ensure clear and reliable […]

October 3rd, 2017|General News Feed|

WIN enables fully integrated single-chip GaAs solutions for 5G RF front-end modules

From Semiconductor Today:

“WIN Semiconductors Corp of Taoyuan City, Taiwan – the largest pure-play compound semiconductor wafer foundry – says that it is enabling fully integrated single-chip solutions for 5G front-end modules with its PIH1-10 gallium arsenide (GaAs) platform. The PIH1-10 process integrates monolithic PIN diodes, capable of power switching through 50GHz, into a 100GHz fT pseudomorphic high-electron-mobility transistor (pHEMT) platform. This technology provides the transmit power performance and lower receiver noise figure required for 5G systems.

WIN says that the versatile technology provides users with multiple pathways to add on-chip functionality and higher integration. In addition to monolithic PIN diodes and high-performance pHEMT devices, the PIH1-10 platform offers linear Schottky diodes for mixers or detectors, as well as enhancement and depletion transistors optimized for logic functionality and bias controls. When combined with RF isolated through-wafer vias, the humidity-resistant technology enables a wafer-level package option for compact chip integration in MIMO functions where available board space is limited.

“The PIH-10 technology leverages WIN’s qualified production techniques and industry-leading manufacturing scale to provide a new platform that can be extended and optimized to address rapidly evolving market requirements,” says senior VP David Danzilio. “Compound semiconductors, and particularly GaAs, remain the technology of choice […]

October 3rd, 2017|General News Feed|

Writing the building blocks of solar technology with lasers


Most of today’s technology in solar energy, telecommunications and microchips is constructed using silicon-based materials. However, in recent years, a new family of semiconducting materials, perovskites, has burst onto the scene, offering promise for new and better technologies. The properties of these materials rival many of the well-established commercial options, while remaining far cheaper and easier to make.

Perovskite is the general name for a material consisting of three chemical components A, B and X, arranged in a specific molecular crystal structure ABX3. One of these perovskites currently being investigated by researchers is formamidinium lead iodide [HC(NH2)2PbI3 or FAPbI3], which holds the world record performance for a perovskite-based solar cell, rivaling silicone-based ones.

Important challenges, however, remain to be resolved regarding the stability of perovskite crystals under real-world conditions. At room temperature, for example, FAPbI3 arranges itself in the yellow coloured delta phase, with little practical value for technological applications. But when heated above 150° C, the material rearranges itself into a different black structure, called the alpha state, before reverting to the delta phase after a few days under ambient conditions. It is this dark alpha state of FAPbI3 that is most interesting for researchers and technology. Until recently, […]

October 3rd, 2017|General News Feed|

Albany, Marcy team up for ‘silicon-carbide corridor’

The Utica area’s next step into its high tech future starts with a 6-inch disc.

Workers at SUNY Polytechnic Institute in Albany are building the nano-sized future of electronic power on round, silicon-carbide wafers — chips that provide power for electronics.

Next year, Quad-C on the SUNY Poly campus in Marcy will start getting shipments of these wafers. General Electric workers will dice them into individual chips. Its partner, Danfoss Silicon Power LLC, will package them into power modules.

The silicon-carbide chips — SiC chips to the technically savvy — operate as switches for power management. They allow for greater efficiency because they can operate at higher temperatures with less cooling than silicon-based chips. That leads to energy savings because they don’t need fans or other cooling devices. So the systems they help run can be simpler and lighter, leading to savings in both energy and cost. These chips will ultimately be used in areas as diverse as aviation, electric cars, renewable energy and medical imaging.

“This is really the future of power electronics,” said Jeffrey Hedrick, vice president of the New York Power Electronics Manufacturing Consortium and a SUNY Poly employee.

Future of Quad-C

Quad-C isn’t operational yet. Contractors are working on the building. […]

October 2nd, 2017|General News Feed|

Solar-Tectic Receives Patent For Novel III-V Tandem Cell

From Compound Semiconductor:

Solar-Tectic LLC has patented a method of making III-V thin-film tandem solar cells with high performance. The patent, US 15/205,316 titled ‘Method of Growing III-V Semiconductor Films for Tandem Solar Cells’ is for high efficiency and cost effective solar cells made on glass or flexible plastic substrates for various industrial applications, such as rooftops to help charge battery-powered electric automobiles (EVs). The technology also looks promising for making LEDs.

The patent (the first ever for a thin III-V layer on crystalline silicon thin-film) covers group III-V elements such as GaAs, and InGaP, for the top layer, as well as all inorganic materials, including, silicon, germanium, etc., for the bottom layer.

In the breakthrough technology here, ultra-thin films of III-V materials and silicon (or germanium) replace expensive, thicker wafers thereby lowering the costs dramatically. The inventor is Ashok Chaudhari, CEO of Solar-Tectic LLC.

III-V tandem (or multi-junction) cells built on wafers such as silicon are currently being developed in labs, with high efficiencies of around ~30 percent. The highest dual-junction cell efficiency (32.8 percent) came from a tandem cell that stacked a layer of GaAs atop crystalline silicon. Manufacturing costs are expensive especially if a germanium wafer is used as the […]

October 2nd, 2017|General News Feed|

Founder of Apple’s Top Chipmaker to Hand Over Reins in June

From Bloomberg:

Taiwan Semiconductor Manufacturing Co. chairman and founder Morris Chang will retire in June next year, handing the helm of the world’s largest producer of made-to-order microchips to the company’s two co-chief executives.

Breaking with tradition, Chang used his retirement announcement to issue a 2017 revenue forecast that surpassed analysts’ estimates. TSMC’s sales growth should be close to 10 percent this year in U.S. dollar terms, he said, a pace that surpasses the roughly 4 percent projected.

Mark Liu will succeed the 86-year-old Chang as chairman, and will have the final say in all business decisions and strategic direction. C.C. Wei will become chief executive officer, orchestrating operations but taking his cues from the board, Chang told reporters at a news conference Monday.

The announcement confirmed longstanding speculation about the heirs-apparent and establishes a formal succession at the manufacturer of chips for Qualcomm Inc. and Apple Inc. — its largest customer. Chang — who stepped down as CEO in 2013 after the board installed Liu and Wei as his lieutenants — left little doubt he plans to step completely away from the corporation he founded in 1987.

“I came to my decision to retire gradually. Of course it had something to do with my age,” Chang said, […]

October 2nd, 2017|General News Feed|

Globalfoundries and Samsung promote FD-SOI in China

From Fudzilla:

Optimistic about growthGlobalfoundries and Samsung are optimistic about chip demand for automotive and IoT applications in China, and are promoting their respective fully-depleted silicon-on-insulator (FD-SOI) process technology there. Globalfoundries CEO Sanjay Jha and ES Jung, EVP & GM of Samsung Foundry, said that they were targeting FD-SOI technology as a low-cost alternative to FinFET .

The Chinese are dead keen on the FD-SOI process because it is much cheaper than FinFET and will help them get a foot in the door of the coming moves to automotive and AI chips . The backing of  Globalfoundries and Samsung has enabled a more complete FD-SOI ecosystem to be developed.

Jha said FD-SOI technology will achieve greater success in China and Globalfoundries has been aggressively promoting its FD-SOI process in the region for the past year. The foundry currently offers its 22nm FD-SOI process (dubbed 22FDX) in China, and will bring a more advanced 12nm FD-SOI process (12FDX) to the market.Jha also disclosed Globalfoundries will hold a “topping out” ceremony to celebrate a major milestone of the construction of its new 12-inch wafer plant in Chengdu at the end of October. The new fab will be ready for volume production in the second half […]

September 29th, 2017|General News Feed|

Perovskite breakthrough could brighten solar industry

From Swiss Info:

Perovskite has great industry potential as a much cheaper, more flexible alternative to conventional silicon-based solar cells. But researchers haven’t been able to produce a perovskite version that’s durable enough to withstand the sun’s rays over time – until now.

Researchers led by Michael Grätzel at the Swiss Federal Institute of Technology in Lausanne (EPFL) have found a way to produce perovskite solar cells (PSCs) that combine high efficiency with stability, paving the commercial way for a cheaper alternative to silicon-based photovoltaic technologies. The innovation has been published in the journal Science.

According to an EPFL press release, the new method yields PSCs that are stable enough to retain more than 95% of their original sunlight-to-electricity conversion efficiency (over 20%), even when exposed to full sunlight at temperatures of 60 degrees Celsius (140 degrees Fahrenheit) for over 1,000 hours.

These properties could help bring PSCs past the point of promising laboratory prototype and towards industry readiness. “This is a major breakthrough in perovskite solar cell research and will pave the way for large-scale commercial deployment of this very promising new photovoltaic technology,” said Grätzel, head of the EPFL Laboratory of Photonics and Interfaces, in a statement on Thursday.

Pushing past a solar […]

September 29th, 2017|General News Feed|

Growing Foundry Market: Less-than-40nm Foundry Market Rapidly Grows

From Business Korea:

As the demand of low power system semiconductor chips related to artificial intelligence (AI) and the Internet of Things (IoT) increases, the less-than-40 nanometer (nm) foundry market is recently rapidly growing.

According to market research firm IC Insights on September 24, the less-than-40nm pure-play foundry market is expected to be worth US$21.5 billion (24.5 trillion won) this year, up 18 percent from last year. The estimate far surpasses 7 percent of the total foundry market growth.

Pure play foundries refer to those foundries who only produces semiconductors on consignment basis, without having any in-house design capabilities including memory chips. Samsung Electronics and Intel are excluded from pure play foundries because they also manufacture semiconductors.

IC Insights expects that the sales of TSMC, the number one leading company in the less-than-40nm pure-play foundry market, will be seven times higher than that of GlobalFoundries, UMC and SIMC, which rank second to fourth in the market, and the share of TSMC in the total sales will reach 10 percent, leading the market.

In fact, there is three years of technical gap in fine processing between SMIC, the fourth biggest player in the market, and TSMC and there are only three companies – Samsung Electronics, […]

September 29th, 2017|General News Feed|