From Semiconductor Engineering:
As chip sizes and complexity continues to grow exponentially at 7nm and below, managing power is becoming much more difficult.
There are a number of factors that come into play at advanced nodes, including more and different types of processors, more chip-package decisions, and more susceptibility to noise of all sorts due to thinner insulation layers and wires. The result is that engineers now need to consider a slew of thermal, packaging and electromagnetic issues that were never serious concerns at previous nodes.
At a high level, these factors dramatically increase the importance of analyzing power from a system level, across multiple different operating scenarios and process corners.
“What is needed is the ability to analyze this large power data and use it to enable timely decisions that can impact the design process,” said Arti Dwivedi, principal technical product manager at ANSYS. “This stresses the need for data analytics-based power solutions with elastic compute and big data architectures.”
This requires more than just tooling, though. “At advanced nodes, low power and high performance designs is a big challenge not just for design styles but also for design flows,” said Jerry Zhao, product management director in the Digital & Signoff Group at […]