Silicon Industry News

Latest news from the semiconductor industry

Chipmakers Look To New Materials

From Semiconductor Engineering:

Graphene, the wonder material rediscovered in 2004, and a host of other two-dimensional materials are gaining ground in manufacturing semiconductors as silicon’s usefulness begins to fade. And while there are a number of compounds in use already, such as gallium arsenide, gallium nitride, and silicon carbide, those materials generally are being confined to specific niche applications.

Transition metal dichalcogenides (TMDCs), a class of 2D materials derived from basic elements—principally tellurium, selenium, sulfur, and oxygen—are being widely explored by researchers for their use as semiconducting materials. These include molybdenum disulfide (MOS2), molybdenum diselenide (MOSe2), molybdenum ditelluride and molybdenum telluride (MOTe2), tungsten disulfide (WS2), and tungsten diselenide (WSe2), which are among the materials being tested for use in chips.

TMDCs are functioning as semiconductors in conjunction with graphene (a carbon allotrope) as an electrical conductor, and monolayer hexagonal boron nitride (also known as white graphene) as an electrical insulator. These materials can be used in electronic devices, energy and harvestingdevices, and for flexible and transparent substrates. TMDCs are also being combined with silicon substrates, to give good old silicon a few more years to shine. And 2D materials can be printed on paper substrates, opening up a whole new field of paper-based […]

December 18th, 2017|General News Feed|

Fujitsu bonds single-crystal diamond and SiC substrate at room temperature, boosting GaN HEMT performance

From Semiconductor Today:

At the IEEE Semiconductor Interface Specialists Conference (SISC2017) in San Diego, CA, USA (6-9 December), Fujitsu Ltd and its subsidiary Fujitsu Laboratories Ltd presented what is claimed to be the first technology for room-temperature bonding of single-crystal diamond to a silicon carbide (SiC) substrate, which are both hard materials but with different coefficients of thermal expansion.

Using this technology for heat dissipation allows high-efficiency cooling of high-power gallium nitride (GaN) high-electron-mobility transistors (HEMTs), enabling stable operations of power amplifiers at high power levels.

In recent years, high-frequency GaN-HEMT power amplifiers have been widely used for long-range radio applications, such as radar and wireless communications. They are also expected to be used in weather radar observing localized heavy rains, for example, or in the forthcoming 5G millimeter-band mobile communications protocols. For these types of radars or wireless communications using the microwave to millimeter-wave bands, by raising the output of the GaN-HEMT power amplifiers used for transmission, the distance that radio waves can propagate will allow the expansion of the observational range of radar while enabling longer and higher-capacity communications.

In GaN-HEMT power amplifiers, some of the input power is converted to heat (Figure 1), which is dispersed into the SiC substrate. […]

December 18th, 2017|General News Feed|

Human touch can feel molecule-thin differences, study reports

From ZME Science:

Our sense of touch comes in very handy. Through it, we can easily discriminate between a wide range of surfaces, from wood, paper and metal to glass and plastics, chiefly due to differences in texture and because every material sucks up the heat from our fingers at different rates. So we understand the ‘how’, but until now we didn’t know how finely tuned our tactile sense is, i.e. what the smallest difference they can pick up on is. Such knowledge is crucial if we are to create life-like prosthetics that can accurately recreate our sense of touch, in the development of virtual and augmented realities, and many other advanced technologies.

New research from the University of California San Diego says that our sense of touch is, in fact, so refined it can pick up on differences of a single layer of molecules
A touching subject
Modern technology such as PCs, game consoles, smartphones, or TVs, let us experience the world more freely and fully than ever before. We can hear and watch events unfolding on the other side of the planet — even on other side of other planets — but these devices don’t allow us to feel what’s happening. Mixing in that ingredient […]

December 15th, 2017|General News Feed|

Complete design of a silicon quantum computer chip unveiled

From phys.org:

Research teams all over the world are exploring different ways to design a working computing chip that can integrate quantum interactions. Now, UNSW engineers believe they have cracked the problem, reimagining the silicon microprocessors we know to create a complete design for a quantum computer chip that can be manufactured using mostly standard industry processes and components.

The new chip design, published in the journal Nature Communications, details a novel architecture that allows quantum calculations to be performed using existing semiconductor components, known as CMOS (complementary metal-oxide-semiconductor) – the basis for all modern chips.

It was devised by Andrew Dzurak, director of the Australian National Fabrication Facility at the University of New South Wales (UNSW), and Dr Menno Veldhorst, lead author of the paper who was a research fellow at UNSW when the conceptual work was done.

“We often think of landing on the Moon as humanity’s greatest technological marvel,” said Dzurak, who is also a Program Leader at Australia’s famed Centre of Excellence for Quantum Computation and Communication Technology (CQC2T). “But creating a microprocessor chip with a billion operating devices integrated together to work like a symphony – that you can carry in your pocket! – is an astounding technical achievement, and one that’s […]

December 15th, 2017|General News Feed|

Researchers develop silicon chip-based quantum photonic devices

From phys.org:

An international team of researchers, affiliated with UNIST has presented a core technology for quantum photonic devices used in quantum information processing. They have proposed combining of quantum dots for generating light and silicon photonic technologies for manipulating light on a single device.

This breakthrough has been led by Professor Je-Hyung Kim in the School of Natural Science at UNIST in collaboration with Professor Edo Waks and a group of researchers at the University of Maryland, United States.

In this study, the research team demonstrated the integration of silicon photonic devices with a solid-state single photon emitter. They used a hybrid approach combining silicon photonic waveguides with InAs/InP quantum dots that act as efficient sources of single photons at telecom wavelengths spanning the O-band and C-band.

In classical computing, a bit is a single piece of information that can exist in two states, zero or one. Quantum computers use quantum bits that can occupy a superposition encompassing both at the same time. There are several potentially fruitful approaches to quantum information processing, including atom, light, and superconducting devices. However, the future of quantum computing, like the quantum state itself, remains uncertain. Professor Kim focuses on the quantum information processing using light. Quantum bits can be implemented using […]

December 13th, 2017|General News Feed|

Fan-Outs vs. TSVs

From Semiconductor Engineering:

Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging.

Fast forward to this month’s 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Calif., and while FO-WLP still dominated, TSVs were included a number of presentations. As advanced packaging begins to mature, packaging is beginning to bifurcate between those applications requiring faster time to market with lots of different kinds of components, which is where fan-out shines, and those requiring blazing fast speed, which is where TSV-based solutions are essential.

FO-WLP really started kicking into gear in 2015 after it was revealed that Apple used the packaging approach in its A9 application processors, which went into that year’s iPhone. Apple utilized TSMC’s Integrated Fan-Out (InFO) packaging technology.

FO-WLP is preferred for mobile electronics. But TSV-based 2.5D and 3D packaging is finding a market in areas such as networking, cloud-based server chips, and increasingly in designs for artificial intelligence and virtual/augmented reality. There are other types of packaging that are being developed and explored by […]

December 13th, 2017|General News Feed|

Monolithic III-nitride on silicon photonics for Internet of Things

From Semiconductor Today:

Nanjing University of Posts and Telecommunications and Zhengzhou University in China have been developing III-nitride technology for visible light communication (VLC) on a monolithic silicon platform [Xumin Gao et al, Optics Letters, vol42, p4853, 2017].

In particular, the team created a system of a light-emitting diode transmitter and photodiode receiver linked by an indium gallium nitride (InGaN) waveguide in aluminium gallium nitride (AlGaN) cladding. Transmission at up to 200Mbits per second (Mb/s) was demonstrated for both in-plane and out-of-plane set ups. The in-plane transmission to an on-chip receiver could be used in practice as a power monitor.

The team sees particular benefit arising for ‘Internet of Things’ applications, along with integrated biomedical analysis systems and monolithic photonic circuits. “From a mass-production point of view, the III-nitride-on-silicon platform offers a feasible approach that is compatible with Si-fab for wafer-level fabrication,” the researchers add.

The device fabrication was performed on 2-inch III-nitride on silicon substrates produced by metal-organic chemical vapor deposition (MOCVD) – see Figure 1. The further processing (Figure 2) consisted of 590nm mesa isolation etch, the formation of an annealed nickel/gold p-contact, etching to the n-contact layer, plasma-enhanced chemical vapor deposition (PECVD) of 200nm silicon dioxide isolation, buffered oxide etch […]

December 13th, 2017|General News Feed|

TSMC to invest record $20bn in advanced 3-nm chips- Nikkei Asian Review

HSINGCHU, Taiwan — Taiwan Semiconductor Manufacturing Co., the world’s biggest contract chipmaker by revenue, is planning to spend more than $20 billion to build the world’s most advanced 3-nanometer chip facility in Taiwan in the early 2020s, according to a senior company executive.

It will be the largest investment the Taiwanese chipmaker has ever made and highlights TSMC’s relentless efforts to stay ahead of competitors including South Korea’s Samsung Electronics and U.S. tech group Intel.

“This past September, we announced our plan for the world’s first 3-nanometer fab located in the Tainan science park [in southern Taiwan]. This fab could cost upwards of $20 billion and represents TSMC’s commitment to drive technology forward,” said Mark Liu, the chipmaker’s co-chief executive, at a company supplier forum on Thursday.

Semiconductors serve as the brain in a wide range of electronic devices including computers and smartphones. The smaller the nanometer measurement, the more advanced the chip — but also the more challenging and expensive to develop.

Apple’s latest smartphone, the iPhone X, uses TSMC’s 10-nanometer technology for its core processor. Apple is TSMC’s No.1 customer, contributing to 17% of the Taiwanese company’s overall revenue in 2016.

TSMC is also looking to produce 7-nanometer chips beginning next year.

The chipmaker’s announcement of the […]

December 12th, 2017|General News Feed|

New silicon structure opens the gate to quantum computers

From phys.org:

In a major step toward making a quantum computer using everyday materials, a team led by researchers at Princeton University has constructed a key piece of silicon hardware capable of controlling quantum behavior between two electrons with extremely high precision. The study was published Dec. 7 in the journal Science.

The team constructed a gate that controls interactions between the electrons in a way that allows them to act as the quantum bits of information, or qubits, necessary for quantum computing. The demonstration of this nearly error-free, two-qubit gate is an important early step in building a more complex quantum computing device from silicon, the same material used in conventional computers and smartphones.

“We knew we needed to get this experiment to work if silicon-based technology was going to have a future in terms of scaling up and building a quantum computer,” said Jason Petta, a professor of physics at Princeton University. “The creation of this high-fidelity two-qubit gate opens the door to larger scale experiments.”

Silicon-based devices are likely to be less expensive and easier to manufacture than other technologies for achieving a quantum computer. Although other research groups and companies have announced quantum devices containing 50 or more qubits, those systems require exotic materials […]

December 12th, 2017|General News Feed|

EVG installs low-temperature plasma activation system at University of Tokyo for III-V on silicon wafer bonding

From Semiconductor Today:

EV Group of St Florian, Austria – a supplier of wafer bonding and lithography equipment for semiconductor, micro-electro-mechanical systems (MEMS), compound semiconductor, power device and nanotechnology applications – has received an order from the University of Tokyo for its EVG810LT plasma activation system for compound semiconductor research.

Installed at the university’s Takagi & Takenaka Laboratory, the EVG810LT augments its research focused on developing novel MOSFET and electronic-photonic integrated circuits (EPICs) using III-V-on-insulator (III-V-OI) and germanium-on-insulator (GeOI) substrates. These are designed to exceed the performance of conventional silicon semiconductors as well as silicon photonics, where III-V materials such as indium phosphide (InP), indium gallium arsenide (InGaAs) and germanium are bonded to silicon wafers. The EVG810LT activates a wafer surface using plasma for low-temperature direct wafer bonding, and has been used by other customers in high-volume manufacturing of silicon-on-insulator (SOI) wafers and backside-illuminated CMOS image sensors.

“The miniaturization of semiconductor devices is reaching its physical limitations, and shrinking transistor (scaling) in line with Moore’s Law is not sufficient enough to address future demands for higher performance of LSI devices,” notes Dr Mitsuru Takenaka, associate professor at the Takagi & Takenaka Lab. “3D integrated circuits with III-V compound semiconductors or germanium stacked […]

December 12th, 2017|General News Feed|

Fins boost prototype vertical GaN transistor to 1200V, sufficient for electric vehicles

From Semiconductor Today:

Commercial gallium nitride (GaN) power devices cannot handle voltages above about 600V, limiting their use to household electronics. But at the Institute of Electrical and Electronics Engineers’ International Electron Devices Meeting (IEDM), researchers from Massachusetts Institute of Technology (MIT), epiwafer and substrate maker IQE plc, Columbia University, IBM and the Singapore-MIT Alliance for Research and Technology presented a new design that, in tests, enabled gallium nitride (GaN) power devices to handle voltages of 1200V.

That is already enough capacity for use in electric vehicles, but the device is a first prototype manufactured in an academic lab. But, since the new device uses a fundamentally different design from existing GaN power electronics, the researchers believe that further work can boost the voltage to 3300-5000V, bringing the efficiencies of GaN to the power electronics in the electrical grid itself.

“All the devices that are commercially available are what are called lateral devices,” says the paper’s senior author Tomás Palacios, who is an MIT professor of electrical engineering and computer science, a member of the Microsystems Technology Laboratories. “So the entire device is fabricated on the top surface of the gallium nitride wafer, which is good for low-power applications like the laptop […]

December 11th, 2017|General News Feed|

Scientist’s accidental exhale leads to improved DNA detector

From phys.org:

Greg Madejski held his breath as he looked into the microscope, trying to weld two fingernail-sized chips together: a tiny chip containing a nanofilter on top of another chip with a DNA sensor.

It was frustrating work. The chips weren’t making good contact with each other. Madejski gently poked at the chips, then peered over the top of the microscope.

And exhaled.

The sudden waft of warm air swept over the nanofilter, transferring it to the sensor -right on target. The “accident” led Madejski to an important insight: the water vapor in his breath had condensed on the device, causing the nanofilter to adhere ever so neatly to the sensor.

“It was like a really high-tech temporary tattoo that I created by accident; lick and stick!” says the PhD student in the lab of James McGrath, a professor of biomedical engineering at the University of Rochester.

And that’s how water vapor became integral to the development and design of a novel device for detecting DNA biomarkers affiliated with disease. Created by McGrath’s lab in collaboration with Professor Vincent Tabard-Cossa and graduate student Kyle Briggs at the University of Ottawa, the device is described in an article published online at Nano Letters. The article, and an image […]

December 11th, 2017|General News Feed|

Demonstrating high performance 2-D monolayer transistors on paper substrates

From Phys.org:

(Tech Xplore)—A pair of researchers, Saungeun Park and Deji Akinwande, with the University of Texas at Austin, recently demonstrated high-performance 2-D monolayer transistors on paper substrates at this year’s International Electron Devices Meeting. At their presentation, they reported creating graphene and molybdenum disulfide transistors on a normal paper substrate and how well they worked—nearly as well as those based on plastic.

Electronics based on paper are still quite rare. They are typically relegated to printed organic electronic devices such as toys and packaging tags. But that may soon change as Park and Akinwande suggest their technique may be used to make devices with more capabilities.

Transistors are typically built using a plastic or semiconductor base. Such materials are chosen because they can withstand the manufacturing process and work optimally once delivered. But both materials cost significantly more than paper, which is why researchers have been eager to find a way to use the naturally grown material as a base, particularly for novel new products that are fast becoming part of the Internet of Things (IoT).

There have been several hurdles preventing the use of paper as a base for transistors: its uneven surface is not conducive to carrying current, it absorbs water, and it burns at […]

December 11th, 2017|General News Feed|

Digitimes Research: 12-inch silicon wafer ASP to rise 20-30% on year in 4Q17

From Digitimes:
The average selling price (ASP) for 12-inch silicon wafers is estimated to surge 20-30% on year in the fourth quarter of 2017, and is expected to enjoy the same annual growth rate in the corresponding quarter of 2018, according to Digitimes Research.
After experiencing an oversupply for 10 years through the first half of 2016, many silicon wafer suppliers have seen fierce competition among wafer foundry houses for their capacities since the second half of 2016. And the suppliers have based the allocation of their capacities on whether foundry houses are willing to sign 2-3-year cooperation pacts and share their blueprints for technology and product development. With this, silicon wafer suppliers will see their profits hit 10-year highs in 2018, Digitimes Research believes.
In terms of sales values and operating profits, Japan-based Shin-Etsu Chemical remains the world’s largest supplier of silicon wafers, followed in sequence by another Japan supplier Sumco, Taiwan supplier GlobalWafers, German-based Siltronic, and Korea’s Sk Siltron. The top-five suppliers command over 90% of the global silicon wafer supplies.
Of the five, Siltronic has posted the highest ASP and is the most capable of expanding its 12-inch silicon wafer capacity. But affected by the long-term oversupply woe, most silicon wafer suppliers […]

December 8th, 2017|General News Feed|

Gallium nitride transistor on silicon with 250GHz cut-off frequency

From Semiconductor Today:

Researchers based in Singapore and USA claim the highest cut-off frequency so far for gallium nitride (GaN) high-electron-mobility transistors (HEMTs) produced on silicon (Si) substrates [Weichuan Xing et al, IEEE Electron Device Letters, published online 13 November 2017]. The devices with indium aluminium nitride (InAlN) barrier layer and gate length of 40nm achieved a cut-off of 250GHz.

The performance compares well with GaN HEMTs produced on silicon carbide (SiC) substrates, which have smaller diameter and are much more expensive. Si-based production methods could open up many commercial opportunities. The III-nitride material system with its wide bandgaps enables higher breakdown fields and high electron saturation velocity with potential applications for high-frequency and high-power performance. The researchers estimate that their devices achieved 1.1x107cm/s electron saturation velocity.

“The next generation of communication systems, including 5G, vehicles and Internet of Things, needs devices operating at mm-wave bands with low cost and high-efficiency”, comment the researchers from Singapore’s Nanyang Technological University, Singapore-MIT Alliance of Research and Technology, Temasek Laboratories Singapore, and Massachusetts Institute of Technology in the USA. The 1cm to 1mm range of wavelengths covers frequencies from 30GHz to 300GHz.

The epitaxial structure (Figure 1) was grown by metal-organic chemical vapor deposition (MOCVD) on […]

December 8th, 2017|General News Feed|

Chemists synthesize narrow ribbons of graphene using only light and heat

From phys.org:

Silicon—the shiny, brittle metal commonly used to make semiconductors—is an essential ingredient of modern-day electronics. But as electronic devices have become smaller and smaller, creating tiny silicon components that fit inside them has become more challenging and more expensive.

Now, UCLA chemists have developed a new method to produce nanoribbons of graphene, next-generation structures that many scientists believe will one day power electronic devices.

This research is published online in the Journal of the American Chemical Society.

The nanoribbons are extremely narrow strips of graphene, the width of just a few carbon atoms. They’re useful because they possess a bandgap, which means that electrons must be “pushed” to flow through them to create electrical current, said Yves Rubin, a professor of chemistry in the UCLA College and the lead author of the research.

“A material that has no bandgap lets electrons flow through unhindered and cannot be used to build logic circuits,” he said.

Rubin and his research team constructed graphene nanoribbons molecule by molecule using a simple reaction based on ultraviolet light and exposure to 600-degree heat.

“Nobody else has been able to do that, but it will be important if one wants to build these molecules on an industrial scale,” said Rubin, who also is a member […]

December 8th, 2017|General News Feed|

Leti integrates hybrid III-V silicon lasers on 200mm wafers using standard CMOS process

From Semiconductor Today:

At the 63rd IEEE International Electron Devices Meeting (IEDM 2017) in San Francisco (4-6 December), micro/nanotechnology R&D center CEA-Leti of Grenoble, France has reported the integration of hybrid III-V silicon lasers on 200mm wafers using a standard CMOS process flow. This shows the way to transitioning away from 100mm wafers and a process based on bulk III-V technology that requires contacts with noble metals and lift-off based patterning, Leti says.

Carried out in the framework of the IRT Nanoelec program (which is headed by Leti), the project demonstrated that the hybrid device’s performance is comparable to the reference device fabricated with the existing process on 100mm wafers. The fabrication flow is fully planar and compatible with large-scale integration on silicon photonic circuits.

CMOS compatibility with silicon photonics lowers fabrication costs and provides access to mature and large-scale facilities, which enables packaging compatibility with CMOS driving circuits, notes Leti.

“Silicon photonic technologies are becoming more mature, but the main limitation of these platforms is the lack of an integrated light source,” says Bertrand Szelag, a co-author of the paper ‘Hybrid III-V/Si DFB Laser Integration on a 200mm Fully CMOS-compatible Silicon Photonics Platform’. “This project showed that a laser can be integrated […]

December 7th, 2017|General News Feed|

Functional ring oscillators based on stacked gate-all-around silicon nanowire transistors

From phys.org:

At this week’s 2017 International Electron Devices Meeting (IEDM), imec, the research and innovation hub in nano-electronics and digital technology, reports on multiple key process optimizations for vertically stacked gate-all-around (GAA) silicon nanowire transistors. The optimized CMOS process flow was then used to integrate, for the first time, the GAA nanowire transistors in a functional ring oscillator. This demonstrator shows the enormous promise this technology holds for realizing the sub-5nm technology nodes.

Gate-all-around (GAA) MOSFETs based on vertically stacked horizontal nanowires or nanosheets are promising candidates to succeed FinFETs in sub-5nm technology nodes, thus extending today’s CMOS technology beyond its scaling limits. This innnovative transistor architecture offers a more aggressive gate pitch scaling than FinFETs because it achieves a better electrostatic control. Moreover, in very scaled standard cells where only one fin device is allowed, nanosheets provide more current per footprint than fins, and thus can drive higher capacitive loads. Finally, integrating nanosheet devices with variable widths in a single platform enables power/performance optimization with high granularity.

As with every disruptive innovation, this new architecture demands for process optimizations. At IEDM, a team of researchers from imec and Applied Materials demonstrated multiple optimizations for the fabrication of stacked silicon nanowire and nanosheet […]

December 7th, 2017|General News Feed|

Transparent Materials with 2D Semiconductors Integrated into See-Through Electronics

From Electronics 360:

See-through electronic devices, like transparent displays, smart windows and concealed circuits, require completely translucent components if users can digitally interact with their perceived surroundings and manipulate this information in real time. KAUST researchers have devised a strategy that helps to integrate transparent conducting metal-oxide contacts with 2D semiconductors into these devices.

Ultrathin semiconductor sheets that are composed of transaction metals associated with chalcogen atoms, like sulfur, selenium and tellurium, present exceptional electronic properties and optical transparency. But, to date, incorporating molybdenum sulphide (Mo52) monolayers into circuits have relied on silicon substrates and metal electrodes, like gold and aluminum. The opacity of these materials has stalled attempts to develop fully transparent 2D electronic devices.

The KAUST team, led by material scientists Xi-Xiang Zhang and Husam Alshareef, has combined MoS2 monolayers with transparent contacts to generate a series of devices and circuits, like transistors, inverters, rectifiers and sensors. The contacts consisted of aluminum-doped zinc oxide (AZO), a low-cost transparent and electrically conductive material that may soon replace the widely used indium-tin oxide.

“We wanted to capitalize on the excellent electronic properties of 2D materials while retaining full transparency in the circuits,” explains Alshareef.

According to Alshareef, the researchers grow the contacts over a […]

December 5th, 2017|General News Feed|

Record low contact resistivity on Ga-doped Ge source/drain contacts for pMOS transistors

From phys.org:

At this week’s 2017 International Electron Devices Meeting (IEDM), imec, the world-leading research and innovation hub in nanoelectronics and digital technology, reports ultralow contact resistivity of 5×10-10Ωcm2 on Gallium (Ga)-doped p-Germanium (Ge) source/drain contacts. The low contact resistivity and high level of Ga activation were achieved after nanosecond laser activation (NLA) at low thermal budget. The results show that highly Ga-doped Ge-rich source/drain contacts provide a promising route for suppressing parasitic source/drain resistance in advanced pMOS devices.

These breakthrough results are important in light of further downscaling of the CMOS source/drain contact area, which is challenged by a parasitic source/drain resistance and results in suboptimal transistor functioning. High dopant activation is known to be an attractive approach for lowering source/drain contact resistance. Traditionally in pMOS devices, Silicon (Si) source/drain contacts with high boron (B) activation are used. But in more advanced pMOS devices, Ge- and SiGe(Sn)-based source/drain are a promising alternative since they introduce beneficial strain. However, the higher the Ge content, the lower the boron activation and solubility in Ge or Ge-rich SiGe.

The new findings result from a comprehensive study of Ga dopant activation in Si, Si0.4Ge0.6 and Ge conducted by imec, KU Leuven (Belgium) and Fudan University (Shangai, […]

December 5th, 2017|General News Feed|

Removing sapphire substrate from light-emitting diodes without cracking

From Semiconductor Today:

Ferdinand-Braun-Institut and Technische Universität Berlin in Germany have developed a fabrication process for deep ultraviolet (DUV) light-emitting diodes (LEDs) that allows laser lift-off (LLO) separation of the sapphire growth substrate without chipping or cracking damage of the device [H K Cho et al, Semicond. Sci. Technol., vol32, p12LT01, 2017]. The LLO was performed at the chip level. The researchers developed a titanium/gold leveling layer that provided support for the fragile epitaxial film during the thermal shock of the LLO and subsequent processes.

The researchers see DUV LEDs as having potential for sterilization, water purification, medical diagnostics, phototherapy and UV curing. Removal of the sapphire substrate, and subsequent surface texturing, is seen as a route to increasing light extraction efficiency, boosting overall external quantum efficiency from the single-digit percentages presently achieved in the DUV region.

The process also allows the use of thin films of planar solder instead of gold stud bumps for mounting, which should improve thermal management in applications. “To the best of our knowledge, LLO of the sapphire substrate from DUV LEDs flip-chip mounted via solder has not yet been reported,” the team writes.

Metal-organic chemical vapor deposition (MOCVD) on (0001) sapphire resulted in a DUV LED structure […]

December 5th, 2017|General News Feed|

Big Challenges, Changes For Debug

From Semiconductor Engineering:

Debugging a chip always has been difficult, but the problem is getting worse at 7nm and 5nm. The number of corner cases is exploding as complexity rises, and some bugs are not even on anyone’s radar until well after devices are already in use by end customers.

An estimated 39% of verification engineering time is spent on debugging activities these days. Verification as a whole accounts for roughly 70% to 80% of total NRE. Still, it’s getting harder to find these bugs as multiple processors and memory types are used to reduce power and optimize performance. Add to that more more functionality, an increasing number of possible use cases and models, and trying to predict all of the things that possibly can go wrong is almost impossible.

As a result, chip architects and engineers are now looking at new approaches to speed up and simplify debug, including continuous monitoring, error correcting strategies, and developing SoCs and ASICs that are inherently easier to debug.

“There are more processor cores, more power domains, and hardware deep-learning neural networks,” said Larry Melling, product management director at Cadence. “Debug of these systems will require more sophistication in root cause identification. Take low-power design for example. […]

December 4th, 2017|General News Feed|

How the smallest damage at the surface of semiconductor crystals develops into large defects

From phys.org:

Using non-destructive imaging methods, a team of scientists at KIT obtains three-dimensional insights into the interior of crystals. They determine important data about line-shaped defects that largely influence the deformation behavior of crystals. These so-called dislocations impede the production of computer chips. As reported in the Physical Review Letters, the scientists combine two X-ray methods with a special type of light microscopy.

Even a few dislocations in silicon wafers can lead to defective computer chips and, hence, to undesired production rejects. “It is therefore important to understand how a minor mechanical surface defect propagates into the depth of the crystal under typical process impacts, such as heat,” says Dr. Daniel Hänschke, physicist of KIT’s Institute for Photon Science and Synchrotron Radiation. His team has succeeded in precisely measuring dislocations and studying their interactions with each other and with external impacts. The scientists analyzed how a single surface defect spreads into an armada of hexagonal defect lines, while completely undamaged areas may remain in the center of such a three-dimensional network. “The resulting collective movement can raise or lower large surface areas on the opposite side of the wafer and cause the formation of steps, which may adversely affect the fabrication and function […]

December 4th, 2017|General News Feed|

Lenses are being reinvented, and cameras will never be the same

From Technology Review:

Lenses are almost as old as civilization itself. The ancient Egyptians, Greeks, and Babylonians all developed lenses made from polished quartz and used them for simple magnification. Later, 17th-century scientists combined lenses to make telescopes and microscopes, instruments that changed our view of the universe and our position within it.

Now lenses are being reinvented by the process of photolithography, which carves subwavelength features onto flat sheets of glass. Today, Alan She and pals at Harvard University in Massachusetts show how to arrange these features in ways that scatter light with greater control than has ever been possible. They say the resulting “metalenses” are set to revolutionize imaging and usher in a new era of optical processing.

Lens making has always been a tricky business. It is generally done by pouring molten glass, or silicon dioxide, into a mold and allowing it to set before grinding and polishing it into the required shape. This is a time-consuming business that is significantly different from the manufacturing processes for light-sensing components on microchips.

So a way of making lenses on chips in the same way would be hugely useful. It would allow lenses to be fabricated in the same plants as other microelectronic components, even […]

December 1st, 2017|General News Feed|

Lightweight, compact VR glasses made possible by large-area microdisplays

From Phys.org:

VR glasses are increasingly popular, but they have usually been heavy and oversized – until now. Large-area microdisplays are expected to change that, because they make it possible to produce ergonomic and lightweight VR glasses. The new OLED displays now reach very high frame rates and achieve extremely high resolutions with “extended full HD.”

The image is crystal clear, and you feel as if you are really walking through the incredible worlds that your VR glasses are conjuring up around you. Until now, however, these glasses have usually been rather heavy and bulky. That is mainly due to the display, which is the key component in every pair of VR glasses. Commercially available VR glasses generally use displays designed for the smartphone market. These displays are cheaply available and employ simple optics to provide a wide field of view. The disadvantage is that they produce pixelated images because of their limited resolution and insufficient pixel density. Modulating LCD and LCOS microdisplays are also used. These are not self-illuminating, however, i.e. an external light source is necessary. In order to produce VR glasses that are light and ergonomic, some manufacturers are therefore already focusing on OLED microdisplays. These are based […]

December 1st, 2017|General News Feed|

Reducing bow of indium gallium phosphide on silicon wafers

From Semiconductor Today:

Researchers based in Singapore and the USA have been working to control the wafer bow of indium gallium phosphide (InGaP) epitaxial layers on 200mm silicon (Si) wafers [Bing Wang et al, Semicond. Sci. Technol., vol32, p125013, 2017].

Wafer bow is caused by stress arising mainly from mismatches of coefficients of thermal expansion between InGaP, or other III-V compound semiconductors, and Si. The bow (more than 200μm in one recent report of gallium arsenide on 300mm Si wafer) is introduced when the material cools after high-temperature epitaxial deposition. Bowing adversely affects wafer-scale processing, particularly for large-diameter substrates. Wafer-scale equipment typically restricts the permitted bow to less than 50μm.

The team from Singapore-MIT Alliance for Research and Technology, Nanyang Technological University in Singapore, and Massachusetts Institute of Technology in the USA used strain engineering to reduce bow in InGaP templates grown on high-quality germanium (Ge) buffers on silicon.

The 200mm (8”) silicon substrate was offcut 6º toward the nearest {111} plane. Epitaxy was by metal-organic chemical vapor deposition (MOCVD). The germanium on silicon template layer was prepared separately in a two-step low/high-temperature process, using germane (GeH4) precursor. Plan-view transmission electron microscopy (PVTEM) and etch pit density (EPD) analysis gave an estimate of […]

December 1st, 2017|General News Feed|

Silicon Wafers: M&A, Price Hikes

From Semiconductor Engineering:

Chipmakers need to keep a close eye on the silicon wafer industry, as the business continues to undergo a number of changes.

On one front, the silicon wafer industry continues to consolidate. Then, after years of suffering from an oversupply and falling prices, many silicon wafer vendors are experiencing tight supply and have begun to raise prices.

Silicon wafers are a fundamental part of the semiconductor business. Every chipmaker needs to buy them in one size or another. Silicon wafer makers produce and sell raw silicon wafers to chipmakers, who process them into chips.

It’s also a tough business that requires a ton of capital and large volumes. Over the past 20 years, the silicon wafer industry has consolidated from more than 20 suppliers in the 1990s to only five large players today.

Last year, for example, Taiwan’s GlobalWafers acquired U.S.-based SunEdison Semiconductor, formerly known as MEMC.

Then, earlier this year, South Korea’s SK Holdings signed a deal to buy a 51% stake in LG Siltron from another Korean vendor, LG Corp., according to several reports. LG Siltron is the world’s fifth largest silicon wafer maker, behind Shin-Etsu, Sumco, GlobalWafers and Siltronic.

“The LG Siltron sale was more of a rescue. Previously, the SK Group rescued Hynix […]

November 30th, 2017|General News Feed|

A nanotransistor made of graphene nanoribbons

From phys.org:

Graphene ribbons that are only a few atoms wide, so-called graphene nanoribbons, have special electrical properties that make them promising candidates for the nanoelectronics of the future. While graphene, a one-dimensional carbon layer, is a conductive material, it can become a semiconductor in the form of nanoribbons. This means that it has a sufficiently large energy or band gap in which no electron states can exist—it can be turned on and off, and thus may become a key component of nanotransistors.

The smallest details in the atomic structure of these graphene bands, however, have massive effects on the size of the energy gap, and thus on how well-suited nanoribbons are as components of transistors. On the one hand, the gap depends on the width of the graphene ribbons, while on the other hand it depends on the structure of the edges. Since graphene consists of equilateral carbon hexagons, the border may have a zigzag or a so-called armchair shape, depending on the orientation of the ribbons. While bands with a zigzag edge behave like metals, i.e. they are conductive, they become semiconductors with the armchair edge.

This poses a major challenge for the production of nanoribbons. If the ribbons are cut from […]

November 30th, 2017|General News Feed|
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    World’s smallest fidget spinner is no bigger than a human hair

World’s smallest fidget spinner is no bigger than a human hair

From ZME Science:

Scientists at the Oak Ridge National Laboratory (ORNL) have taken 3-D printing to the next level. Through a novel technique, they were able to print the world’s smallest fidget spinner. It can easily fit within the width of a human hair — virtually invisible to the naked eye.

The computer-aided design of the fidget spinner was first sliced into multiple digital layers. Then just one drop of a special liquid is added to a piece of silicon wafer and then loaded into a nanoscribe machine. This device is somewhat similar to a 3D printer. However, unlike a 3D printer, it oozes liquid plastic from a nozzle, using a laser to raster its way through the liquid and create a pattern, then turning the liquid into a solid. The laser shapes the liquid only in its strongest, most concentrated point known as the focal point, allowing the researchers to achieve a stunning level of precision.

Beyond the fidget spinner craze, the ORNL researchers have demonstrated more serious applications, including a technique that could be used to fabricate microswimmers and tetrapod devices that precisely deliver drugs into the human body.
“We felt like it [the fidget spinner] would be an interesting demonstration for younger people who may not know that […]

November 30th, 2017|General News Feed|

Downstream players scrambling to build up inventories amid tight wafer supply

From Digitimes:
The semiconductor supply chain – especially chip vendors – as well as downstream distribution channels and end-market customers, are rushing to pile up inventories by the end of 2017, seeking to secure better sales performance in 2018 amid lingering tight supply of upstream materials, parts and components, although market prospects for end-market devices remain unclear for next year, according to industry sources.
The ongoing round of supply shortfall was mainly triggered by tight silicon wafer supply. As China will fully gear up to bolster its wafer foundry sector in 2018, global silicon wafer supply is expected to stay short of demand in the coming 2-3 years. This is why wafer suppliers, chipmakers, and downstream customers are actively stocking up more products, lest the shortage of silicon wafers and even chips should affect their sales performance in the coming year, the sources said.
In fact, many types of chips are already in tight supply, including DRAM, NOR flash, MOSFET, MCU and LCD driver chips, and even suppliers of LED chips, sapphire substrates, and passive components are reportedly raising their sales prices. Facing tight supply of upstream materials, parts and components, downstream customers might be forced to offer higher prices to secure […]

November 29th, 2017|General News Feed|