Silicon Valley Microelectronics provides a wide variety of lithography and other wafer patterning solutions to the semiconductor and MEMS industries. Standard test patterns are available for CMP, etch, clean, and medical device manufacturing markets on glass and silicon substrates. In addition to our standard test pattern offerings, SVM accepts custom wafer patterning projects based upon end-user design with an option to provide engineering CAD and mask manufacture.

  • Materials: Silicon, glass
  • Wafer diameters: 50mm to 300mm
  • Lithography tools: Scanner, stepper, proximity/contact aligner, e-beam
  • Technology nodes: 65nm, 90nm, 130nm, 180nm, 250nm and larger
  • Photoresist: 193nm, 248nm(DUV), I-Line
  • Etch: Wet, RIE, DRIE
  • CMP: W, Cu, Al, oxide, TEOS
  • Metrology: SEM, cross section, e-test etc.

Test Reticles:

  • CMP dishing and erosion
  • Surface trench isolation (STI)
  • Damascene and dual damascene
  • Line/Space arrays
  • Via arrays
  • Daisy chain
  • Memory patterns
  • E-testable structures
  • TSV 100 SiVia wafer
  • TSV 1060 SiVia wafer
  • TSV 530 SiVia wafer

Specialty Products:

Precious metals: Au, Pd, Ag, Pt
Thick photoresist

­­­­­­­­­­­­­­­­­TSV 100 SiVia

The through-silicon via (TSV) is etched with excellent sidewall surface roughness from the center of the wafer to the edge of the wafer aligned to the notch.

All TSV wafers are etched on a 10μm to 100μm via etch pattern layout for a 200mm wafer.

The electroplated copper layer is 10,000Å followed by 2μm Cu seed layer and 1000Å titanium liner on TEOS.

SVM offers through-silicon via (TSV) wafers with a via depth of 100μm and a diameter of 50μm.

Cross Section

Si vias, before Cu seed after Cu seed
Si vias, before Cu seed(1) aft_ Cu seed

 

TSV 1060 SiVia

The through-silicon via (TSV) is etched with excellent sidewall surface roughness from the center of the wafer to the edge of the wafer aligned to the notch.
All through-silicon vias are etched on a 200mm wafer.

The electroplated copper layer is 10,000Å followed by 2μm Cu seed layer and 1000Å titanium liner on TEOS.

SVM offers Through-Silicon Via (TSV) wafers with the ability to electrical test vias with diameters of 10μm, 20μm, 30μm, 40μm, 45μm, 50μm, 55μm, and 60μm.


Please CONTACT SVM to speak with a member of our knowledgeable team for further information on lithography services, to discuss your current requirements or to request a quote.


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