Silicon on insulator wafers are most common in microelectromechanical systems (MEMS) and advanced complementary metal–oxide–semiconductor (CMOS) integrated circuit fabrication, and can improve many of the processes that more traditional silicon wafers are used in. These wafers provide a manufacturing solution which helps reduce power and heat while increasing the speed performance of a device. Silicon on insulator wafers are a three layer material stack composed of the following: an active layer of prime quality silicon (device layer) over a buried oxide layer (box) of electrically insulating silicon dioxide, over a bulk silicon support wafer (handle). SOI wafers are unique products for specific end-user applications.
Silicon on Insulator Fabrication Process
There are 3 primary ways to fabricate silicon on insulator wafers, and each one produces a substrate with slightly different film properties. A member of the SVM sales team will determine which fabrication method is best for your project’s requirements by submitting your requirements through our contact form or via email.
Bonded & Etchback SOI (BESOI)
Some applications favor this method because there is no implantation, which minimizes damage done to the substrate surface. There are also few free charge carriers, which can improve the long term performance of a device. Due to the nature of CMP and wafer grinding processes, this is generally used to manufacture SOI wafers with a device layer >2μm. SVM can manufacture these wafers in any diameter from 3″ (76.2mm) to 8″ (200mm).
- Two starting wafers undergo thermal oxidation to grow silicon dioxide (thermal oxide) layers. When in the furnace, oxide will grow on all sides of the wafer unless one side is covered with a resist.
- Once the oxide layer is sufficiently thick, the wafers are bonded together at the oxide film. Roughness in the atomic structure of silicon dioxide allows the wafers to partially bond at room temperature, although to solidify the bonds, they are baked at about 1100°C.
- After bonding, the wafers undergo the ‘etching’ stage, using methods more common in wafer thinning, rather than lithographic etching. The wafers undergo chemical mechanical polishing (CMP) or etching in order to remove the majority of one of the substrates, leaving just a thin layer of silicon above the silicon dioxide film. To improve uniformity during the etching process, an etch-stop limits how thin the wafer will get. To use an etch-stop, one of the starting wafers is doped heavily p-type (>1019 cm-3) via implant or epitaxy prior to bonding. The doped wafer is then exposed to a highly selective etchant that removes the doped portion of the wafer. This allows the dopants to predetermine the thickness and uniformity of the top silicon layer.
Separation by IMplantation of OXygen (SIMOX)
This process is often preferred to other fabrications techniques for silicon on insulator wafers because of its ability to precisely control the thickness of the oxide layer. For some applications, nitrogen or oxynitride can replace oxygen without adverse affects, although the vast majority of applications require oxygen.
- The process is fairly simple, and just requires implantation of a large number of oxygen ions below the surface of a wafer.
- Oxygen ions implant into the silicon by an ion beam. The energy used to implant the oxygen ions determines the depth of the silicon dioxide layer, as well as the thickness of the subsequent silicon overlayer (device layer).
- Without changing other variables, a wafer implanted with oxygen ions travelling 200keV will produce a wafer with a silicon dioxide layer of ~.5μm (500nm), and a top silicon layer of ~.3μm (300nm).
- If the wafer stays at room temperature and pressure, an extra amorphous silicon layer will form on the surface. In order to prevent this, the wafer temperature must not dip below 600°C at any point during the fabrication process.
- After implanting the oxide layer, the wafer bakes for several hours at ~1300°C. This solidifies the film and produces a uniform buried oxide layer throughout the entire wafer.
This method combines the repeatability of SIMOX with the flexibility of BESOI, allowing different oxide film thicknesses while maintaining a high uniformity across different wafers. In contrast to BESOI, the bonded wafer can be recycled, which makes this method slightly more cost effective. Due to the cleaving process of SmartCut SOI wafers, these can produce device layers as thin as 50nm (500Å, .05μm)
- To start, a silicon dioxide film is grown on the wafer surface.
- Wafer is implanted with hydrogen ions. This will later be used to create the device layer.
- After implanting the wafer, it’s bonded with a handle wafer to create a stack, similarly to BESOI.
- The wafers undergo two thermal processing steps to produce the final SOI substrate:
- 600°C bake splits the wafer at the peak hydrogen implant profile.
- 1100°C bake strengthens the bond between the two wafers.
- CMP (polishing) reduces roughness where hydrogen ions split the wafer. This generally produces a SEMI standard roughness specification of ≤2Å.
Sample SVM Silicon on Insulator (SOI) Specifications*:
*If your requirements are outside of these specifications, SVM will gladly custom manufacture SOI wafers to fit your project’s requirements. For different device layer thicknesses and custom SOI wafers, there may be a minimum order quantity of 1 cassette (25 wafers) for certain specifications.
Why choose SVM?
- Single side polish and double side polish
- Prototype and production volumes
- Consistent, reliable production supply line
- Competitive pricing