From Electronics 360:

Imec, in collaboration with Soitec, announced a successful sequential 3D front-end integration process by stacking two device layers on one another on a 300 mm wafer. The debut occurred at the annual Imec Technology Forum USA.

This vertical integration process, also named sequential-3D integration (S3D), promises to continue the benefits offered by semiconductor scaling, overcoming the constraints of geometrical scaling while maintaining the benefits of functional scaling through the vertical 3D integration.

A critical challenge of S3D is the control of the thermal budget. To preserve optimal device operation the top device layer must be processed at temperatures below 525° C. The top thermal budget needs to be reduced to avoid degradation of the bottom devices, the bottom interconnects and the bonding interface. These limitations are overcome with the implementation of junction-less transistors on the top-layer which decreases the fabrication complexity and provides sufficient device reliability.

Read more: SEMICON West 2018: Imec and Soitec Demonstrate Sequential 3D Planar Device with High Reliability at Low Temperature | Electronics360 reposted by Silicon Valley Microelectronics, Inc.